Datasheet > CY7C145

CY7C145

更新时间： 2024-01-04 12:10:30

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
20页	609K
描述
8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY

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CY7C145 数据手册

CY7C144 CY7C1458K

with SEM, INT, BUSY

x 8/9 Dual-Port Static RAM

CY7C144

CY7C145

8K x 8/9 Dual-Port Static RAM

with SEM, INT, BUSY

are included on the CY7C144/5 to handle situations when

multiple processors access the same piece of data. Two ports

are provided permitting independent, asynchronous access

for reads and writes to any location in memory. The

CY7C144/5 can be utilized as a standalone 64/72-Kbit

dual-port static RAM or multiple devices can be combined in

order to function as a 16/18-bit or wider master/slave dual-port

static RAM. An M/S pin is provided for implementing 16/18-bit

or wider memory applications without the need for separate

master and slave devices or additional discrete logic. Appli-

cation areas include interprocessor/multiprocessor designs,

Features

• TrueDual-Portedmemorycellsthatallowsimultaneous

reads of the same memory location

• 8K x 8 organization (CY7C144)

• 8K x 9 organization (CY7C145)

• 0.65-micron CMOS for optimum speed/power

• High-speed access: 15ns

• Low operating power: I_CC= 160 mA (max.)

• Fully asynchronous operation

• Automatic power-down

communications

status

buffering,

and

dual-port

video/graphics memory.

Each port has independent control pins: chip enable (CE),

read or write enable (R/W), and output enable (OE). Two flags,

BUSY and INT, are provided on each port. BUSY signals that

the port is trying to access the same location currently being

accessed by the other port. The interrupt flag (INT) permits

communication between ports or systems by means of a mail

box. The semaphores are used to pass a flag, or token, from

one port to the other to indicate that a shared resource is in

use. The semaphore logic is comprised of eight shared

latches. Only one side can control the latch (semaphore) at

any time. Control of a semaphore indicates that a shared

resource is in use. An automatic power-down feature is

controlled independently on each port by a chip enable (CE)

pin or SEM pin.

• TTL compatible

• Master/Slave select pin allows bus width expansion to

16/18 bits or more

• Busy arbitration scheme provided

• Semaphores included to permit software handshaking

between ports

• INT flag for port-to-port communication

• Available in 68-pin PLCC, 64-pin and 80-pin TQFP

• Pb-Free packages available

Functional Description

The CY7C144 and CY7C145 are high-speed CMOS 8K x 8

and 8K x 9 dual-port static RAMs. Various arbitration schemes

Logic Block Diagram

R/W

(7C145) I/O

I/O (7C145)

I/O

CONTROL

I/O

CONTROL

I/O

[1, 2]

BUSY

12L

12R

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS

DECODER

INTERRUPT

SEMAPHORE

ARBITRATION

R/W

SEM

[2]

INT

INT [2]

M/S

Notes:

1. BUSY is an output in master mode and an input in slave mode.

2. Interrupt: push-pull output and requires no pull-up resistor.

Cypress Semiconductor Corporation

Document #: 38-06034 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 6, 2005

12 3 4 5 6 7...20

中文翻译

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与CY7C145相关器件

型号	品牌	获取价格	描述	数据表
CY7C145-15AC	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C145-15ACT	CYPRESS	获取价格	暂无描述
CY7C145-15AXC	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY
CY7C145-15AXCT	CYPRESS	获取价格	Multi-Port SRAM, 8KX9, 15ns, CMOS, PQFP80
CY7C145-15JC	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C145-15JCT	CYPRESS	获取价格	Dual-Port SRAM, 8KX9, 15ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C145-25AC	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C145-25AC	ROCHESTER	获取价格	8KX9 DUAL-PORT SRAM, 25ns, PQFP80, PLASTIC, LCC-80
CY7C145-25AI	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C145-25JC	CYPRESS	获取价格	8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy

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