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CY7C145-15AXCT

更新时间： 2024-02-18 15:11:08
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
20页 609K
描述
Multi-Port SRAM, 8KX9, 15ns, CMOS, PQFP80

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CY7C145-15AXCT 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：LCC包装说明：PLASTIC, LCC-68
针数：68Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.8Is Samacsys：N
最长访问时间：15 ns其他特性：SEMAPHORE
I/O 类型：COMMONJESD-30 代码：S-PQCC-J68
JESD-609代码：e0长度：24.2316 mm
内存密度：73728 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：9功能数量：1
端口数量：2端子数量：68
字数：8192 words字数代码：8000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：8KX9
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC68,1.0SQ封装形状：SQUARE
封装形式：CHIP CARRIER并行/串行：PARALLEL
峰值回流温度（摄氏度）：225电源：5 V
认证状态：Not Qualified座面最大高度：5.08 mm
最大待机电流：0.015 A最小待机电流：4.5 V
子类别：SRAMs最大压摆率：0.22 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：24.2316 mm
Base Number Matches：1

CY7C145-15AXCT 数据手册

 浏览型号CY7C145-15AXCT的Datasheet PDF文件第2页浏览型号CY7C145-15AXCT的Datasheet PDF文件第3页浏览型号CY7C145-15AXCT的Datasheet PDF文件第4页浏览型号CY7C145-15AXCT的Datasheet PDF文件第5页浏览型号CY7C145-15AXCT的Datasheet PDF文件第6页浏览型号CY7C145-15AXCT的Datasheet PDF文件第7页 
CY7C144 CY7C1458K  
with SEM, INT, BUSY  
x 8/9 Dual-Port Static RAM  
CY7C144  
CY7C145  
8K x 8/9 Dual-Port Static RAM  
with SEM, INT, BUSY  
are included on the CY7C144/5 to handle situations when  
multiple processors access the same piece of data. Two ports  
are provided permitting independent, asynchronous access  
for reads and writes to any location in memory. The  
CY7C144/5 can be utilized as a standalone 64/72-Kbit  
dual-port static RAM or multiple devices can be combined in  
order to function as a 16/18-bit or wider master/slave dual-port  
static RAM. An M/S pin is provided for implementing 16/18-bit  
or wider memory applications without the need for separate  
master and slave devices or additional discrete logic. Appli-  
cation areas include interprocessor/multiprocessor designs,  
Features  
• TrueDual-Portedmemorycellsthatallowsimultaneous  
reads of the same memory location  
• 8K x 8 organization (CY7C144)  
• 8K x 9 organization (CY7C145)  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 15ns  
• Low operating power: ICC = 160 mA (max.)  
• Fully asynchronous operation  
• Automatic power-down  
communications  
status  
buffering,  
and  
dual-port  
video/graphics memory.  
Each port has independent control pins: chip enable (CE),  
read or write enable (R/W), and output enable (OE). Two flags,  
BUSY and INT, are provided on each port. BUSY signals that  
the port is trying to access the same location currently being  
accessed by the other port. The interrupt flag (INT) permits  
communication between ports or systems by means of a mail  
box. The semaphores are used to pass a flag, or token, from  
one port to the other to indicate that a shared resource is in  
use. The semaphore logic is comprised of eight shared  
latches. Only one side can control the latch (semaphore) at  
any time. Control of a semaphore indicates that a shared  
resource is in use. An automatic power-down feature is  
controlled independently on each port by a chip enable (CE)  
pin or SEM pin.  
• TTL compatible  
• Master/Slave select pin allows bus width expansion to  
16/18 bits or more  
• Busy arbitration scheme provided  
• Semaphores included to permit software handshaking  
between ports  
• INT flag for port-to-port communication  
• Available in 68-pin PLCC, 64-pin and 80-pin TQFP  
• Pb-Free packages available  
Functional Description  
The CY7C144 and CY7C145 are high-speed CMOS 8K x 8  
and 8K x 9 dual-port static RAMs. Various arbitration schemes  
Logic Block Diagram  
R/W  
L
R/W  
R
CE  
OE  
CE  
OE  
L
L
R
R
(7C145) I/O  
I/O (7C145)  
8R  
8L  
I/O  
7L  
I/O  
7R  
I/O  
CONTROL  
I/O  
CONTROL  
I/O  
0L  
I/O  
0R  
[1, 2]  
[1, 2]  
BUSY  
BUSY  
L
R
A
12L  
0L  
A
A
12R  
0R  
MEMORY  
ARRAY  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
A
INTERRUPT  
SEMAPHORE  
ARBITRATION  
CE  
L
CE  
OE  
R
R
OE  
L
R/W  
R/W  
L
R
SEM  
SEM  
R
L
[2]  
INT  
INT [2]  
R
L
M/S  
Notes:  
1. BUSY is an output in master mode and an input in slave mode.  
2. Interrupt: push-pull output and requires no pull-up resistor.  
Cypress Semiconductor Corporation  
Document #: 38-06034 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 6, 2005  
1234567...20

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