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CY7C144E-55AXC PDF预览

CY7C144E-55AXC

更新时间： 2024-01-14 23:24:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
23页 417K
描述
Dual-Port SRAM, 8KX8, 55ns, CMOS, PQFP64, TQFP-64

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CY7C144E-55AXC 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-64针数：64
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.79
最长访问时间：55 nsI/O 类型：COMMON
JESD-30 代码：S-PQFP-G64JESD-609代码：e4
长度：14 mm内存密度：65536 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：8
湿度敏感等级：3功能数量：1
端口数量：2端子数量：64
字数：8192 words字数代码：8000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：8KX8
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP64,.66SQ,32
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：5 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.0005 A
最小待机电流：4.5 V子类别：SRAMs
最大压摆率：0.275 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

CY7C144E-55AXC 数据手册

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CY7C144E  
8K × 8 Dual-Port Static RAM  
with SEM, INT, BUSY  
8K  
× 8 Dual-Port Static RAM with SEM, INT, BUSY  
Features  
Functional Description  
■ True dual-ported memory cells that enable simultaneous reads  
of the same memory location  
The CY7C144E is a high speed CMOS 8K × 8 dual port static  
RAM. Various arbitration schemes are included on the  
CY7C144E to handle situations when multiple processors  
access the same piece of data. Two ports are provided permitting  
independent, asynchronous access for reads and writes to any  
location in memory. The CY7C144E can be used as a  
standalone 64-Kbit dual-port static RAM or multiple devices can  
be combined in order to function as a 16-bit or wider  
master/slave dual-port static RAM. An M/S pin is provided for  
implementing 16-bit or wider memory applications without the  
need for separate master and slave devices or additional  
■ 8K × 8 organization (CY7C144E)  
■ 0.35-micron CMOS for optimum speed and power  
■ High-speed access: 15 ns  
■ Low operating power: ICC = 180 mA (typical),  
standby ISB3 = 0.05 mA (typical)  
■ Fully asynchronous operation  
■ Automatic power-down  
■ TTL compatible  
discrete  
logic.  
Application  
areas  
include  
interprocessor/multiprocessor designs, communications status  
buffering, and dual-port video / graphics memory.  
Each port has independent control pins: chip enable (CE), read  
or write enable (R/W), and output enable (OE). Two flags, BUSY  
and INT, are provided on each port. BUSY signals that the port  
is trying to access the same location currently being accessed  
by the other port. The interrupt flag (INT) permits communication  
between ports or systems by means of a mail box. The  
semaphores are used to pass a flag, or token, from one port to  
the other to indicate that a shared resource is in use. The  
semaphore logic is comprised of eight shared latches. Only one  
side can control the latch (semaphore) at any time. Control of a  
semaphore indicates that a shared resource is in use. An  
automatic power-down feature is controlled independently on  
each port by a chip enable (CE) pin or SEM pin.  
■ Master/slaveselectpinenablesbuswidthexpansionto16-bits  
or more  
■ Busy arbitration scheme provided  
■ Semaphores included to permit software handshaking  
between ports  
■ INT flag for port-to-port communication  
■ Available in 68-pin PLCC and 64-pin TQFP  
■ Pb-free packages available  
For a complete list of related documentation, click here.  
Logic Block Diagram  
R/W  
L
R/W  
R
CE  
OE  
CE  
OE  
L
L
R
R
I/O  
7L  
I/O  
I/O  
7R  
0R  
I/O  
CONTROL  
I/O  
CONTROL  
I/O  
0L  
[1, 2]  
[1, 2]  
BUSY  
BUSY  
L
R
A
12L  
0L  
A
A
12R  
0R  
MEMORY  
ARRAY  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
A
INTERRUPT  
SEMAPHORE  
ARBITRATION  
CE  
L
CE  
OE  
R
R
OE  
L
R/W  
R/W  
L
R
SEM  
L
SEM  
R
L
[2]  
INT  
INT [2]  
R
M/S  
Notes  
1. BUSY is an output in master mode and an input in slave mode.  
2. Interrupt: push-pull output and requires no pull-up resistor.  
Cypress Semiconductor Corporation  
Document Number: 001-63982 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised January 5, 2018  
 
 
 
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中文翻译

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CY7C144E-55AXC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C144AV-25AXC CYPRESS

类似代替

 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
CY7C144AV-25AC CYPRESS

类似代替

 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM
CY7C144-55AXC CYPRESS

类似代替

 8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY

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CY7C144V-15JCR CYPRESS

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 		Multi-Port SRAM, 8KX8, 15ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C144V-25JCR CYPRESS

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 		Multi-Port SRAM, 8KX8, 25ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C145 CYPRESS

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 		8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY
CY7C145-15AC CYPRESS

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 		8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C145-15ACT CYPRESS

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 		暂无描述
CY7C145-15AXC CYPRESS

获取价格

 		8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY
CY7C145-15AXCT CYPRESS

获取价格

 		Multi-Port SRAM, 8KX9, 15ns, CMOS, PQFP80
CY7C145-15JC CYPRESS

获取价格

 		8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C145-15JCT CYPRESS

获取价格

 		Dual-Port SRAM, 8KX9, 15ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C145-25AC CYPRESS

获取价格

 		8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy

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