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CY7C144AV-25JC PDF预览

CY7C144AV-25JC

更新时间: 2024-12-01 05:19:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
20页 546K
描述
3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM

CY7C144AV-25JC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:LCC包装说明:PLASTIC, LCC-68
针数:68Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
Factory Lead Time:1 week风险等级:5.3
最长访问时间:25 nsI/O 类型:COMMON
JESD-30 代码:S-PQCC-J68JESD-609代码:e0
长度:24.2316 mm内存密度:65536 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
功能数量:1端口数量:2
端子数量:68字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC68,1.0SQ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified座面最大高度:5.08 mm
最大待机电流:0.00005 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.165 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:24.2316 mm
Base Number Matches:1

CY7C144AV-25JC 数据手册

 浏览型号CY7C144AV-25JC的Datasheet PDF文件第2页浏览型号CY7C144AV-25JC的Datasheet PDF文件第3页浏览型号CY7C144AV-25JC的Datasheet PDF文件第4页浏览型号CY7C144AV-25JC的Datasheet PDF文件第5页浏览型号CY7C144AV-25JC的Datasheet PDF文件第6页浏览型号CY7C144AV-25JC的Datasheet PDF文件第7页 
CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 4K/8K/16K/32K  
Dual-Port Static RAM  
x 8/9  
CY7C138AV/144AV/006AV  
CY7C139AV/145AV/016AV  
CY7C007AV/017AV  
3.3V 4K/8K/16K/32K x 8/9  
Dual-Port Static RAM  
Features  
• True Dual-Ported memory cells which allow  
• Automatic power-down  
simultaneous access of the same memory location  
• Expandabledatabusto16/18bitsormoreusingMaster/  
Slave chip select when using more than one device  
• 4K/8K/16K/32K x 8 organizations  
(CY7C0138AV/144AV/006AV/007AV)  
• On-chip arbitration logic  
• 4K/8K/16K/32K x 9 organizations  
(CY7C0139AV/145AV/016AV/017AV)  
• Semaphores included to permit software handshaking  
between ports  
• 0.35-micron CMOS for optimum speed/power  
• High-speed access: 20/25 ns  
• Low operating power  
• INT flag for port-to-port communication  
• Pin select for Master or Slave  
• Commercial and Industrial Temperature Ranges  
— Active: ICC = 115 mA (typical)  
— Standby: ISB3 = 10 µA (typical)  
• Fully asynchronous operation  
• Available in 68-pin PLCC (all) and 64-pin TQFP  
(7C006AV & 7C144AV)  
• Pb-Free packages available  
Logic Block Diagram  
R/WL  
CEL  
R/WR  
CER  
OEL  
OER  
8/9  
[1]  
8/9  
[1]  
I/O0L–I/O7/8L  
I/O0R–I/O7/8R  
I/O  
Control  
I/O  
Control  
12–15  
12–15  
[2]  
[2]  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
A0L–A11–14L  
A0R–A  
11–14R  
RAM Array  
12–15  
12–15  
[2]  
[2]  
A0L–A11–14L  
A0R–A  
11–14R  
CEL  
CER  
OER  
Interrupt  
Semaphore  
Arbitration  
OEL  
R/WL  
SEML  
R/WR  
SEMR  
[3]BUSYR  
INTR  
[3]  
BUSYL  
INTL  
M/S  
For the most recent information, visit the Cypress web site at www.cypress.com  
Notes:  
1. I/O –I/O for x8 devices; I/O –I/O for x9 devices.  
0
7
0
8
2. A –A for 4K devices; A –A for 8K devices; A –A for 16K devices; A –A for 32K devices;  
0
11  
0
12  
0
13  
0
14  
3. BUSY is an output in master mode and an input in slave mode.  
Cypress Semiconductor Corporation  
Document #: 38-06051 Rev. *C  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised June 6, 2005  

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