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CY7C1399B-15ZXI PDF预览

CY7C1399B-15ZXI

更新时间： 2024-11-05 05:09:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 185K
描述
256K(32K x 8) Static RAM

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CY7C1399B-15ZXI 数据手册

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CY7C1399B  
256K(32K x 8) Static RAM  
active LOW Output Enable (OE) and three-state drivers. The  
device has an automatic power-down feature, reducing the  
power consumption by more than 95% when deselected.  
Features  
• Single 3.3V power supply  
• Ideal for low-voltage cache memory applications  
• High speed  
An active LOW Write Enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location  
addressed by the address present on the address pins (A0  
through A14). Reading the device is accomplished by selecting  
the device and enabling the outputs, CE and OE active LOW,  
while WE remains inactive or HIGH. Under these conditions,  
the contents of the location addressed by the information on  
address pins is present on the eight data input/output pins.  
— 10/12/15 ns  
• Low active power  
— 216 mW (max.)  
• Low-power alpha immune 6T cell  
• Plastic SOJ and TSOP packaging  
Functional Description[1]  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and Write Enable  
(WE) is HIGH. The CY7C1399B is available in 28-pin standard  
300-mil-wide SOJ and TSOP Type I packages.  
The CY7C1399B is a high-performance 3.3V CMOS Static  
RAM organized as 32,768 words by 8 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE) and  
Logic Block Diagram  
Pin Configurations  
SOJ  
Top View  
A
A
V
28  
27  
26  
1
2
3
4
5
6
5
CC  
WE  
6
A
A
7
A
4
A
3
8
25  
24  
A
9
A
2
A
10  
A
11  
A
12  
23  
22  
A
1
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
7
8
9
10  
11  
12  
13  
OE  
A
0
CE  
I/O  
I/O  
0
1
2
3
4
5
6
21  
20  
19  
18  
17  
INPUT BUFFER  
A
A
13  
A
14  
7
0
I/O  
I/O  
I/O  
A
0
1
2
6
5
4
1
I/O  
A
2
16  
15  
A
I/O  
I/O  
3
A
GND  
14  
4
3
32K x 8  
ARRAY  
A
5
A
6
A
7
A
8
A
9
CE  
WE  
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
7
OE  
Selection Guide  
1399B-10  
1399B-12  
1399B-15  
1399B-20  
Unit  
ns  
Maximum Access Time  
10  
60  
12  
55  
15  
50  
20  
45  
Maximum Operating Current  
mA  
µA  
Maximum CMOS Standby Current  
500  
50  
500  
50  
500  
50  
500  
50  
L
µA  
Note:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05071 Rev. *D  
• 3901 North First Street  
• San Jose, CA 95134  
•
408-943-2600  
Revised July 11, 2005  
1234567...10

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CY7C1399B-15ZXI 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1399BN-15ZXI CYPRESS

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