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CY7C1399BL-15ZXC PDF预览

CY7C1399BL-15ZXC

更新时间: 2024-11-05 05:09:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 内存集成电路静态存储器光电二极管
页数 文件大小 规格书
10页 185K
描述
256K(32K x 8) Static RAM

CY7C1399BL-15ZXC 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSOP包装说明:8 X 13.40 MM, LEAD FREE, TSOP1-28
针数:28Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
Factory Lead Time:1 week风险等级:5.51
最长访问时间:15 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G28JESD-609代码:e4
长度:11.8 mm内存密度:262144 bit
内存集成电路类型:CACHE SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:28字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP1
封装等效代码:TSSOP28,.53,22封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.00002 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.05 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.55 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:8 mm

CY7C1399BL-15ZXC 数据手册

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CY7C1399B  
256K(32K x 8) Static RAM  
active LOW Output Enable (OE) and three-state drivers. The  
device has an automatic power-down feature, reducing the  
power consumption by more than 95% when deselected.  
Features  
• Single 3.3V power supply  
• Ideal for low-voltage cache memory applications  
• High speed  
An active LOW Write Enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location  
addressed by the address present on the address pins (A0  
through A14). Reading the device is accomplished by selecting  
the device and enabling the outputs, CE and OE active LOW,  
while WE remains inactive or HIGH. Under these conditions,  
the contents of the location addressed by the information on  
address pins is present on the eight data input/output pins.  
— 10/12/15 ns  
• Low active power  
— 216 mW (max.)  
• Low-power alpha immune 6T cell  
• Plastic SOJ and TSOP packaging  
Functional Description[1]  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and Write Enable  
(WE) is HIGH. The CY7C1399B is available in 28-pin standard  
300-mil-wide SOJ and TSOP Type I packages.  
The CY7C1399B is a high-performance 3.3V CMOS Static  
RAM organized as 32,768 words by 8 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE) and  
Logic Block Diagram  
Pin Configurations  
SOJ  
Top View  
A
A
V
28  
27  
26  
1
2
3
4
5
6
5
CC  
WE  
6
A
A
7
A
4
A
3
8
25  
24  
A
9
A
2
A
10  
A
11  
A
12  
23  
22  
A
1
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
7
8
9
10  
11  
12  
13  
OE  
A
0
CE  
I/O  
I/O  
0
1
2
3
4
5
6
21  
20  
19  
18  
17  
INPUT BUFFER  
A
A
13  
A
14  
7
0
I/O  
I/O  
I/O  
A
0
1
2
6
5
4
1
I/O  
A
2
16  
15  
A
I/O  
I/O  
3
A
GND  
14  
4
3
32K x 8  
ARRAY  
A
5
A
6
A
7
A
8
A
9
CE  
WE  
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
7
OE  
Selection Guide  
1399B-10  
1399B-12  
1399B-15  
1399B-20  
Unit  
ns  
Maximum Access Time  
10  
60  
12  
55  
15  
50  
20  
45  
Maximum Operating Current  
mA  
µA  
Maximum CMOS Standby Current  
500  
50  
500  
50  
500  
50  
500  
50  
L
µA  
Note:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05071 Rev. *D  
• 3901 North First Street  
• San Jose, CA 95134  
408-943-2600  
Revised July 11, 2005  

CY7C1399BL-15ZXC 替代型号

型号 品牌 替代类型 描述 数据表
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