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CY7C1399BL-12ZC PDF预览

CY7C1399BL-12ZC

更新时间： 2024-11-04 22:25:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 153K
描述
32K x 8 3.3V Static RAM

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CY7C1399BL-12ZC 数据手册

 浏览型号CY7C1399BL-12ZC的Datasheet PDF文件第2页浏览型号CY7C1399BL-12ZC的Datasheet PDF文件第3页浏览型号CY7C1399BL-12ZC的Datasheet PDF文件第4页浏览型号CY7C1399BL-12ZC的Datasheet PDF文件第5页浏览型号CY7C1399BL-12ZC的Datasheet PDF文件第6页浏览型号CY7C1399BL-12ZC的Datasheet PDF文件第7页 
C1399B  
CY7C1399B  
32K x 8 3.3V Static RAM  
active LOW Output Enable (OE) and three-state drivers. The  
device has an automatic power-down feature, reducing the  
power consumption by more than 95% when deselected.  
Features  
• Single 3.3V power supply  
• Ideal for low-voltage cache memory applications  
• High speed  
An active LOW Write Enable signal (WE) controls the writing/  
reading operation of the memory. When CE and WE inputs are  
both LOW, data on the eight data input/output pins (I/O0  
through I/O7) is written into the memory location addressed by  
the address present on the address pins (A0 through A14).  
Reading the device is accomplished by selecting the device  
and enabling the outputs, CE and OE active LOW, while WE  
remains inactive or HIGH. Under these conditions, the con-  
tents of the location addressed by the information on address  
pins is present on the eight data input/output pins.  
— 10/12/15 ns  
• Low active power  
— 216 mW (max.)  
• Low-power alpha immune 6T cell  
• Plastic SOJ and TSOP packaging  
Functional Description[1]  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and Write Enable  
(WE) is HIGH. The CY7C1399B is available in 28-pin standard  
300-mil-wide SOJ and TSOP Type I packages.  
The CY7C1399B is a high-performance 3.3V CMOS Static  
RAM organized as 32,768 words by 8 bits. Easy memory ex-  
pansion is provided by an active LOW Chip Enable (CE) and  
Logic Block Diagram  
Pin Configurations  
SOJ  
Top View  
A
A
V
CC  
28  
27  
26  
1
2
3
4
5
6
5
WE  
6
A
A
7
A
4
A
3
8
25  
24  
A
9
A
2
A
10  
A
11  
A
12  
23  
22  
A
1
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
7
8
9
10  
11  
12  
13  
OE  
A
0
0
1
2
3
4
5
6
21  
20  
19  
18  
17  
INPUT BUFFER  
A
13  
A
14  
CE  
I/O  
A
0
7
I/O  
I/O  
I/O  
I/O  
I/O  
A
1
0
1
2
6
5
4
A
2
16  
15  
A
3
I/O  
I/O  
A
4
GND  
14  
3
32K x 8  
ARRAY  
A
5
A
6
A
7
A
8
A
9
CE  
WE  
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
7
OE  
Selection Guide  
1399B-10  
1399B-12  
1399B-15  
1399B-20  
Maximum Access Time (ns)  
10  
60  
12  
55  
15  
50  
20  
45  
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (µA)  
500  
50  
500  
50  
500  
50  
500  
50  
L
Note:  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05071 Rev. *C  
Revised June 19, 2001  
1234567...10

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CY7C1399BL-12ZC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1399B-12ZCT CYPRESS

完全替代

 Cache SRAM, 32KX8, 12ns, CMOS, PDSO28, 8 X 13.40 MM, TSOP1-28
CY7C1399BL-12ZXC CYPRESS

功能相似

 256K(32K x 8) Static RAM
CY7C1399B-12ZC CYPRESS

功能相似

 32K x 8 3.3V Static RAM

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型号 品牌 获取价格 描述 数据表
CY7C1399BL-12ZCT CYPRESS

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 		Cache SRAM, 32KX8, 12ns, CMOS, PDSO28, 8 X 13.40 MM, TSOP1-28
CY7C1399BL-12ZXC CYPRESS

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 		256K(32K x 8) Static RAM
CY7C1399BL-12ZXCT CYPRESS

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 		Cache SRAM, 32KX8, 12ns, CMOS, PDSO28, 8 X 13.40 MM, LEAD FREE, TSOP1-28
CY7C1399BL-12ZXCT ROCHESTER

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 		32KX8 CACHE SRAM, 12ns, PDSO28, 8 X 13.40 MM, LEAD FREE, TSOP1-28
CY7C1399BL-15VC CYPRESS

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 		32K x 8 3.3V Static RAM
CY7C1399BL-15VC ROCHESTER

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 		32KX8 CACHE SRAM, 15ns, PDSO28, 0.300 INCH, SOJ-28
CY7C1399BL-15VXC CYPRESS

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 		256K(32K x 8) Static RAM
CY7C1399BL-15VXC ROCHESTER

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 		32KX8 CACHE SRAM, 15ns, PDSO28, 0.300 INCH, LEAD FREE, SOJ-28
CY7C1399BL-15VXCT CYPRESS

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 		Cache SRAM, 32KX8, 15ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, SOJ-28
CY7C1399BL-15ZC CYPRESS

获取价格

 		32K x 8 3.3V Static RAM

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