Datasheet > CY7C1383BV25-100BGI

CY7C1383BV25-100BGI

更新时间： 2024-11-14 04:17:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
26页	799K
描述
Standard SRAM, 1MX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

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CY7C1383BV25

CY7C1381BV25

512K x 36 / 1M x 18 Flow-Thru SRAM

registers controlled by a positive-edge-triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining Chip Enable (CE), Burst Control

Inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,

BWc, BWd,and BWe), and Global Write (GW).

Features

• Fast access times: 7.5, 8.5, 10 ns

• Fast clock speed: 117, 100, 83 MHz

• Provide high-performance 2-1-1-1 access rate

• Optimal for depth expansion

Asynchronous inputs include the output enable (OE) and burst

mode control (MODE). The data outputs (Q), enabled by OE,

are also asynchronous.

• 2.5V ± 5% power supply

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Chip enable for address pipeline

• Address, data, and control registers

• Internally self-timed Write Cycle

Addresses and chip enables are registered with either

Address Status Processor (ADSP) or Address Status

Controller (ADSC) input pins. Subsequent burst addresses

can be internally generated as controlled by the Burst Advance

Pin (ADV).

• Burst control pins (interleaved or linear burst

sequence)

• Automatic power-down available using ZZ mode or CE

deselect

• High-density, high-speed packages

• JTAG boundary scan for BGA packaging version

Address, data inputs, and write controls are registered on-chip

to initiate self-timed WRITE cycle. WRITE cycles can be one

to four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BWa

controls DQ1–DQ8 and DP1. BWb controls DQ9–DQ16 and

DP2. BWc controls DQ17–DQ24and DP3. BWd controls

DQ25–DQ32 and DP4. BWa, BWb BWc, and BWd can be

active only with BWe being LOW. GW being LOW causes all

bytes to be written. WRITE pass-through capability allows

written data available at the output for the immediately next

Read cycle. This device also incorporates pipelined enable

circuit for easy depth expansion without penalizing system

performance.

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low power CMOS designs using advanced single

layer polysilicon, three-layer metal technology. Each memory

cell consists of six transistors.

The CY7C1381BV25 and CY7C1383BV25 SRAMs integrate

524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

All inputs and outputs of the CY7C1381BV25 and the

CY7C1383BV25 are JEDEC standard JESD8-5-compatible.

Selection Guide

117 MHz

7.5

100 MHz

8.5

83 Mhz

Unit

Maximum Access Time

Maximum Operating Current

Commercial

210

190

160

Maximum CMOS Standby Current

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05249 Rev. *A

Revised January 18, 2003

12 3 4 5 6 7...26

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与CY7C1383BV25-100BGI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1383BV25-100BZI	CYPRESS	获取价格	Standard SRAM, 1MX18, 8.5ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1383BV25-117AC	CYPRESS	获取价格	Standard SRAM, 1MX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1383BV25-117BZC	CYPRESS	获取价格	暂无描述
CY7C1383BV25-133BGC	CYPRESS	获取价格	Standard SRAM, 1MX18, 6.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
CY7C1383BV25-83BGC	CYPRESS	获取价格	Standard SRAM, 1MX18, 10ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1383BV25-83BZC	CYPRESS	获取价格	Standard SRAM, 1MX18, 10ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1383BV25-83BZI	CYPRESS	获取价格	Standard SRAM, 1MX18, 10ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1383C	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383C-100AC	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383C-100AI	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM

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