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CY7C1383CV25-100AXI

更新时间： 2024-09-25 13:07:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
35页	501K
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CY7C1381CV25

CY7C1383CV25

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Features

Functional Description^[1]

• Supports 133-MHz bus operations

• 512K X 36/1M X 18 common I/O

• 2.5V +/–5% core power supply (V_DD

The CY7C1381CV25/CY7C1383CV25 is a 2.5V, 512K x 36

and 1M x 18 Synchronous Flow through SRAMs, respectively

designed to interface with high-speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

)

• 2.5V I/O supply (V_DDQ

)

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

— 7.5 ns (117-MHz version)

— 8.5 ns (100-MHz version)

addresses, all data inputs, address-pipelining Chip Enable

[2]

(

), depth-expansion Chip Enables (CE and

), Burst

CE₃

CE₁

Control inputs (

), Write Enables

(

ADV

BW_x

and

• Provide high-performance 2-1-1-1 access rate

ADSC ADSP

), and Global Write (

BWE

). Asynchronous

and

inputs

• User-selectable burst counter supporting Intel^

(

)

and the ZZ pin

include the Output Enable

Pentium^interleaved or linear burst sequences

The CY7C1381CV25/CY7C1383CV25 allows either inter-

leaved or linear burst sequences, selected by the MODE input

pin. A HIGH selects an interleaved burst sequence, while a

LOW selects a linear burst sequence. Burst accesses can be

initiated with the Processor Address Strobe (ADSP) or the

cache Controller Address Strobe (ADSC) inputs. Address

advancement is controlled by the Address Advancement

(ADV) input.

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Offered in JEDEC-standard 100-pin TQFP,119-ball BGA

and 165-ball fBGA packages

• JTAG boundary scan for BGA and fBGA packages

• “ZZ” Sleep Mode option

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (

) or

ADSP

Address Strobe Controller (

) are active. Subsequent

ADSC

burst addresses can be internally generated as controlled by

the Advance pin ( ).

ADV

The CY7C1381CV25/CY7C1383CV25 operates from a +2.5V

core power supply. All outputs also operate with a +2.5 supply.

All

inputs

and

outputs

are

JEDEC-standard

JESD8-5-compatible.

Selection Guide

133 MHz

117 MHz

7.5

100 MHz

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

6.5

210

8.5

175

190

Notes:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05241 Rev. *B

Revised April 19, 2004

12 3 4 5 6 7...35

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与CY7C1383CV25-100AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1383CV25-100BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383CV25-100BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383CV25-100BZC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383CV25-100BZI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383CV25-117AC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383CV25-117AI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383CV25-117BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383CV25-117BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383CV25-117BZC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383CV25-117BZI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

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