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CY7C1383CV25-117BZC PDF预览

CY7C1383CV25-117BZC

更新时间： 2024-11-13 04:01:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
35页 501K
描述
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

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中文翻译

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CY7C1383CV25-117BZC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：13 X 15 MM, 1.20 MM HEIGHT, FBGA-165针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
最长访问时间：7.5 ns其他特性：FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：117 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e0
长度：15 mm内存密度：18874368 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：220电源：2.5 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.07 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.19 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

CY7C1383CV25-117BZC 数据手册

 浏览型号CY7C1383CV25-117BZC的Datasheet PDF文件第2页浏览型号CY7C1383CV25-117BZC的Datasheet PDF文件第3页浏览型号CY7C1383CV25-117BZC的Datasheet PDF文件第4页浏览型号CY7C1383CV25-117BZC的Datasheet PDF文件第5页浏览型号CY7C1383CV25-117BZC的Datasheet PDF文件第6页浏览型号CY7C1383CV25-117BZC的Datasheet PDF文件第7页 
CY7C1381CV25  
CY7C1383CV25  
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM  
Features  
Functional Description[1]  
• Supports 133-MHz bus operations  
• 512K X 36/1M X 18 common I/O  
• 2.5V +/–5% core power supply (VDD  
The CY7C1381CV25/CY7C1383CV25 is a 2.5V, 512K x 36  
and 1M x 18 Synchronous Flow through SRAMs, respectively  
designed to interface with high-speed microprocessors with  
minimum glue logic. Maximum access delay from clock rise is  
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the  
first address in a burst and increments the address automati-  
cally for the rest of the burst access. All synchronous inputs  
are gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
)
• 2.5V I/O supply (VDDQ  
)
• Fast clock-to-output times  
— 6.5 ns (133-MHz version)  
— 7.5 ns (117-MHz version)  
— 8.5 ns (100-MHz version)  
addresses, all data inputs, address-pipelining Chip Enable  
[2]  
(
), depth-expansion Chip Enables (CE and  
), Burst  
CE3  
CE1  
2
Control inputs (  
,
,
), Write Enables  
(
ADV  
BWx  
and  
,
• Provide high-performance 2-1-1-1 access rate  
ADSC ADSP  
), and Global Write (  
BWE  
). Asynchronous  
GW  
and  
inputs  
• User-selectable burst counter supporting Intel  
(
)
and the ZZ pin  
OE  
.
include the Output Enable  
Pentiuminterleaved or linear burst sequences  
The CY7C1381CV25/CY7C1383CV25 allows either inter-  
leaved or linear burst sequences, selected by the MODE input  
pin. A HIGH selects an interleaved burst sequence, while a  
LOW selects a linear burst sequence. Burst accesses can be  
initiated with the Processor Address Strobe (ADSP) or the  
cache Controller Address Strobe (ADSC) inputs. Address  
advancement is controlled by the Address Advancement  
(ADV) input.  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
• Asynchronous output enable  
• Offered in JEDEC-standard 100-pin TQFP,119-ball BGA  
and 165-ball fBGA packages  
• JTAG boundary scan for BGA and fBGA packages  
• “ZZ” Sleep Mode option  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (  
) or  
ADSP  
Address Strobe Controller (  
) are active. Subsequent  
ADSC  
burst addresses can be internally generated as controlled by  
the Advance pin ( ).  
ADV  
The CY7C1381CV25/CY7C1383CV25 operates from a +2.5V  
core power supply. All outputs also operate with a +2.5 supply.  
All  
inputs  
and  
outputs  
are  
JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
133 MHz  
117 MHz  
7.5  
100 MHz  
Unit  
ns  
mA  
mA  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
6.5  
210  
70  
8.5  
175  
70  
190  
70  
Notes:  
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.  
3,  
2
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05241 Rev. *B  
Revised April 19, 2004  
1234567...35

中文翻译

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