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CY7C1383D-100BGC PDF预览

CY7C1383D-100BGC

更新时间： 2024-11-13 05:19:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
29页 466K
描述
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

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中文翻译

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CY7C1383D-100BGC 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 2.40 MM HEIGHT, BGA-119
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.84Is Samacsys：N
最长访问时间：8.5 ns其他特性：FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：100 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B119JESD-609代码：e0
长度：22 mm内存密度：18874368 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：119字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：220电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：2.4 mm
最大待机电流：0.07 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.175 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

CY7C1383D-100BGC 数据手册

 浏览型号CY7C1383D-100BGC的Datasheet PDF文件第2页浏览型号CY7C1383D-100BGC的Datasheet PDF文件第3页浏览型号CY7C1383D-100BGC的Datasheet PDF文件第4页浏览型号CY7C1383D-100BGC的Datasheet PDF文件第5页浏览型号CY7C1383D-100BGC的Datasheet PDF文件第6页浏览型号CY7C1383D-100BGC的Datasheet PDF文件第7页 
CY7C1381D  
CY7C1383D  
PRELIMINARY  
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM  
Features  
Functional Description[1]  
• Supports 133-MHz bus operations  
• 512K × 36/1M × 18 common I/O  
• 3.3V –5% and +10% core power supply (VDD  
The CY7C1381D/CY7C1383D is a 3.3V, 512K x 36 and 1 Mbit  
18 Synchronous Flow-through SRAMs, respectively  
x
designed to interface with high-speed microprocessors with  
minimum glue logic. Maximum access delay from clock rise is  
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the  
first address in a burst and increments the address automati-  
cally for the rest of the burst access. All synchronous inputs  
are gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
)
• 2.5V or 3.3V I/O supply (VDDQ  
• Fast clock-to-output time  
— 6.5 ns (133-MHz version)  
— 8.5 ns (100-MHz version)  
)
addresses, all data inputs, address-pipelining Chip Enable  
[2]  
• Provide high-performance 2-1-1-1 access rate  
(
), depth-expansion Chip Enables (CE and  
), Burst  
CE3  
CE1  
2
• User-selectable burst counter supporting Intel  
Control inputs (  
,
,
), Write Enables  
(
ADV  
BWx  
and  
,
ADSC ADSP  
Pentiuminterleaved or linear burst sequences  
), and Global Write (  
BWE  
). Asynchronous  
GW  
and  
inputs  
(
)
and the ZZ pin  
OE  
.
include the Output Enable  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
• Asynchronous output enable  
The CY7C1381D/CY7C1383D allows either interleaved or  
linear burst sequences, selected by the MODE input pin. A  
HIGH selects an interleaved burst sequence, while a LOW  
selects a linear burst sequence. Burst accesses can be  
initiated with the Processor Address Strobe (ADSP) or the  
cache Controller Address Strobe (ADSC) inputs. Address  
advancement is controlled by the Address Advancement  
(ADV) input.  
• Offered in JEDEC-standard lead-free 100-pin TQFP  
,119-ball BGA and 165-ball fBGA packages  
• JTAG boundary scan for BGA and fBGA packages  
• “ZZ” Sleep Mode option  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (  
) or  
ADSP  
Address Strobe Controller (  
) are active. Subsequent  
ADSC  
burst addresses can be internally generated as controlled by  
the Advance pin ( ).  
ADV  
The CY7C1381D/CY7C1383D operates from a +3.3V core  
power supply while all outputs may operate with either a +2.5  
or +3.3V supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
133 MHz  
6.5  
100 MHz  
8.5  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
210  
70  
175  
70  
mA  
mA  
Notes:  
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.  
3,  
2
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05544 Rev. *A  
Revised November 2, 2004  
1234567...29

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CY7C1383D-100BGI CYPRESS

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CY7C1383D-100BGXC CYPRESS

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 		18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383D-100BGXI CYPRESS

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 		18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383D-100BZC CYPRESS

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 		18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383D-100BZI CYPRESS

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 		18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383D-100BZXC CYPRESS

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 		18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383D-100BZXI CYPRESS

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 		18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383D-117AI CYPRESS

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 		Cache SRAM, 1MX18, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1383D-117BGC CYPRESS

获取价格

 		Cache SRAM, 1MX18, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1383D-133AC CYPRESS

获取价格

 		Cache SRAM, 1MX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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