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CY7C1383D-133AXI PDF预览

CY7C1383D-133AXI

更新时间： 2024-11-13 05:19:27
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赛普拉斯 - CYPRESS 静态存储器
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29页 1219K
描述
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

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CY7C1383D-133AXI 数据手册

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CY7C1381D, CY7C1381F  
CY7C1383D, CY7C1383F  
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM  
Features  
Functional Description [1]  
• Supports 133 MHz bus operations  
• 512K × 36 and 1M × 18 common IO  
The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a  
3.3V, 512K x 36 and 1M x 18 synchronous flow through  
SRAMs,  
designed  
to  
interface  
with  
high-speed  
• 3.3V core power supply (VDD  
)
microprocessors with minimum glue logic. Maximum access  
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit  
on-chip counter captures the first address in a burst and  
increments the address automatically for the rest of the burst  
access. All synchronous inputs are gated by registers  
controlled by a positive edge triggered clock input (CLK). The  
synchronous inputs include all addresses, all data inputs,  
address pipelining chip enable (CE1), depth-expansion chip  
enables (CE2 and CE3 [2]), burst control inputs (ADSC, ADSP,  
and ADV), write enables (BWx, and BWE), and global write  
(GW). Asynchronous inputs include the output enable (OE)  
and the ZZ pin.  
• 2.5V or 3.3V IO supply (VDDQ  
• Fast clock-to-output time  
— 6.5 ns (133 MHz version)  
)
• Provides high performance 2-1-1-1 access rate  
• User selectable burst counter supporting Intel® Pentium®  
interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
• Asynchronous output enable  
The  
CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F  
• CY7C1381D/CY7C1383D available in JEDEC-standard  
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball  
FBGA package. CY7C1381F/CY7C1383F available in  
Pb-free and non Pb-free 119-ball BGA package  
allows interleaved or linear burst sequences, selected by the  
MODE input pin. A HIGH selects an interleaved burst  
sequence, while a LOW selects a linear burst sequence. Burst  
accesses can be initiated with the processor address strobe  
(ADSP) or the cache controller address strobe (ADSC) inputs.  
Address advancement is controlled by the address  
advancement (ADV) input.  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• ZZ sleep mode option  
Addresses and chip enables are registered at rising edge of  
clock when address strobe processor (ADSP) or address  
strobe controller (ADSC) are active. Subsequent burst  
addresses can be internally generated as controlled by the  
advance pin (ADV).  
The  
CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F  
operates from a +3.3V core power supply while all outputs  
operate with a +2.5V or +3.3V supply. All inputs and outputs  
are JEDEC-standard and JESD8-5-compatible.  
Selection Guide  
133 MHz  
6.5  
100 MHz  
8.5  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
210  
70  
175  
mA  
mA  
70  
Notes:  
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.  
2. CE CE are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.  
3,  
2
Cypress Semiconductor Corporation  
Document #: 38-05544 Rev. *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised Feburary 07, 2007  
[+] Feedback  
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CY7C1383D-133AXI 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1383KV33-133AXI CYPRESS

完全替代

 18-Mbit (512K × 36/1M × 18) Flow-Through SR
CY7C1383D-133AXC CYPRESS

类似代替

 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

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