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CY7C1383BV25-83BZC PDF预览

CY7C1383BV25-83BZC

更新时间： 2024-11-13 15:30:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
26页 799K
描述
Standard SRAM, 1MX18, 10ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165

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CY7C1383BV25-83BZC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：13 X 15 MM, 1.20 MM HEIGHT, FBGA-165针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
最长访问时间：10 ns其他特性：FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：83 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B165JESD-609代码：e0
长度：15 mm内存密度：18874368 bit
内存集成电路类型：STANDARD SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：165字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TBGA
封装等效代码：BGA165,11X15,40封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：220电源：2.5 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.03 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.16 mA
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：13 mm
Base Number Matches：1

CY7C1383BV25-83BZC 数据手册

 浏览型号CY7C1383BV25-83BZC的Datasheet PDF文件第2页浏览型号CY7C1383BV25-83BZC的Datasheet PDF文件第3页浏览型号CY7C1383BV25-83BZC的Datasheet PDF文件第4页浏览型号CY7C1383BV25-83BZC的Datasheet PDF文件第5页浏览型号CY7C1383BV25-83BZC的Datasheet PDF文件第6页浏览型号CY7C1383BV25-83BZC的Datasheet PDF文件第7页 
CY7C1383BV25  
CY7C1381BV25  
512K x 36 / 1M x 18 Flow-Thru SRAM  
registers controlled by a positive-edge-triggered Clock Input  
(CLK). The synchronous inputs include all addresses, all data  
inputs, address-pipelining Chip Enable (CE), Burst Control  
Inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,  
BWc, BWd,and BWe), and Global Write (GW).  
Features  
• Fast access times: 7.5, 8.5, 10 ns  
• Fast clock speed: 117, 100, 83 MHz  
• Provide high-performance 2-1-1-1 access rate  
• Optimal for depth expansion  
Asynchronous inputs include the output enable (OE) and burst  
mode control (MODE). The data outputs (Q), enabled by OE,  
are also asynchronous.  
• 2.5V ± 5% power supply  
• Common data inputs and data outputs  
• Byte Write Enable and Global Write control  
• Chip enable for address pipeline  
• Address, data, and control registers  
• Internally self-timed Write Cycle  
Addresses and chip enables are registered with either  
Address Status Processor (ADSP) or Address Status  
Controller (ADSC) input pins. Subsequent burst addresses  
can be internally generated as controlled by the Burst Advance  
Pin (ADV).  
• Burst control pins (interleaved or linear burst  
sequence)  
• Automatic power-down available using ZZ mode or CE  
deselect  
• High-density, high-speed packages  
• JTAG boundary scan for BGA packaging version  
Address, data inputs, and write controls are registered on-chip  
to initiate self-timed WRITE cycle. WRITE cycles can be one  
to four bytes wide as controlled by the write control inputs.  
Individual byte write allows individual byte to be written. BWa  
controls DQ1–DQ8 and DP1. BWb controls DQ9–DQ16 and  
DP2. BWc controls DQ17–DQ24and DP3. BWd controls  
DQ25–DQ32 and DP4. BWa, BWb BWc, and BWd can be  
active only with BWe being LOW. GW being LOW causes all  
bytes to be written. WRITE pass-through capability allows  
written data available at the output for the immediately next  
Read cycle. This device also incorporates pipelined enable  
circuit for easy depth expansion without penalizing system  
performance.  
Functional Description  
The Cypress Synchronous Burst SRAM family employs  
high-speed, low power CMOS designs using advanced single  
layer polysilicon, three-layer metal technology. Each memory  
cell consists of six transistors.  
The CY7C1381BV25 and CY7C1383BV25 SRAMs integrate  
524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced  
synchronous peripheral circuitry and a two-bit counter for  
internal burst operation. All synchronous inputs are gated by  
All inputs and outputs of the CY7C1381BV25 and the  
CY7C1383BV25 are JEDEC standard JESD8-5-compatible.  
Selection Guide  
117 MHz  
7.5  
100 MHz  
8.5  
83 Mhz  
10  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Commercial  
210  
190  
160  
30  
mA  
mA  
Maximum CMOS Standby Current  
30  
30  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05249 Rev. *A  
Revised January 18, 2003  
1234567...26

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