Datasheet > 存储 > SRAM> CY7C1383C-117AI

CY7C1383C-117AI

更新时间： 2024-09-24 22:34:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
36页	563K
描述
18-Mb (512K x 36/1M x 18) Flow-Through SRAM

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CY7C1383C-117AI 数据手册

CY7C1381C

CY7C1383C

18-Mb (512K x 36/1M x 18) Flow-Through SRAM

Features

Functional Description^[1]

• Supports 133-MHz bus operations

• 512K X 36/1M X 18 common I/O

The CY7C1381C/CY7C1383C is a 3.3V, 512K x 36 and 1M x

18 Synchronous Flowthrough SRAMs, respectively designed

to interface with high-speed microprocessors with minimum

glue logic. Maximum access delay from clock rise is 6.5 ns

(133-MHz version). A 2-bit on-chip counter captures the first

address in a burst and increments the address automatically

for the rest of the burst access. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

• 3.3V –5% and +10% core power supply (V_DD

)

• 2.5V or 3.3V I/O supply (V_DDQ

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

)

— 7.5 ns (117-MHz version)

— 8.5 ns (100-MHz version)

addresses, all data inputs, address-pipelining Chip Enable

[2]

(

), depth-expansion Chip Enables (CE and

), Burst

CE₃

• Provide high-performance 2-1-1-1 access rate

CE₁

Control inputs (

), Write Enables

(

ADV

BW_x

• User-selectable burst counter supporting Intel^

and

ADSC ADSP

Pentium^interleaved or linear burst sequences

), and Global Write (

BWE

). Asynchronous

and

inputs

(

)

and the ZZ pin

include the Output Enable

• Separate processor and controller address strobes

• Synchronous self-timed write

The CY7C1381C/CY7C1383C allows either interleaved or

linear burst sequences, selected by the MODE input pin. A

HIGH selects an interleaved burst sequence, while a LOW

selects a linear burst sequence. Burst accesses can be

initiated with the Processor Address Strobe (ADSP) or the

cache Controller Address Strobe (ADSC) inputs. Address

advancement is controlled by the Address Advancement

(ADV) input.

• Asynchronous output enable

• OfferedinJEDEC-standard100-pinTQFP,119-ballBGA

and 165-ball fBGA packages

• JTAG boundary scan for BGA and fBGA packages

• “ZZ” Sleep Mode option

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (

) or

ADSP

Address Strobe Controller (

) are active. Subsequent

ADSC

burst addresses can be internally generated as controlled by

the Advance pin ( ).

ADV

The CY7C1381C/CY7C1383C operates from a +3.3V core

power supply while all outputs may operate with either a +2.5

or +3.3V supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

133 MHz

117 MHz

7.5

100 MHz

8.5

Unit

Maximum Access Time

Maximum Operating Current

6.5

210

190

175

Maximum CMOS Standby Current

Notes:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05238 Rev. *B

Revised February 26, 2004

12 3 4 5 6 7...36

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与CY7C1383C-117AI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1383C-117BGC	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383C-117BGI	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383C-117BZC	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383C-117BZI	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383C-133AC	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383C-133BGC	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383C-133BZC	CYPRESS	获取价格	18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383CV25	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383CV25-100AC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383CV25-100AI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

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