Datasheet > CY7C1382DV33

CY7C1382DV33

更新时间： 2024-11-14 01:14:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
33页	1088K
描述
18-Mbit (512 K Ã 36/1 M Ã 18) Pipelined SRAM

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CY7C1382DV33 数据手册

CY7C1380DV33

CY7C1382DV33

18-Mbit (512 K × 36/1 M × 18)

Pipelined SRAM

18-Mbit (512

K × 36/1 M × 18) Pipelined SRAM

Features

Functional Description

■ Supports bus operation up to 200 MHz

■ Available speed grades is 200 MHz

■ Registered inputs and outputs for pipelined operation

■ 3.3 V core power supply

The CY7C1380DV33/CY7C1382DV33 SRAM integrates

524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced

synchronous peripheral circuitry and a two-bit counter for

internal burst operation. All synchronous inputs are gated by

registers controlled by a positive edge triggered clock input

(CLK). The synchronous inputs include all addresses, all data

inputs, address-pipelining chip enable (CE₁), depth-expansion

chip enables (CE₂and CE₃^[1]), burst control inputs (ADSC,

ADSP, and ADV), write enables (BW_X, and BWE), and global

write (GW). Asynchronous inputs include the output enable (OE)

and the ZZ pin.

■ 2.5 V or 3.3 V I/O power supply

■ Fast clock-to-output times

❐ 3 ns (for 200 MHz device)

■ Provides high performance 3-1-1-1 access rate

Addresses and chip enables are registered at rising edge of

clock when address strobe processor (ADSP) or address strobe

controller (ADSC) are active. Subsequent burst addresses can

be internally generated as they are controlled by the advance pin

(ADV).

■ User selectable burst counter supporting Intel^Pentium^®

interleaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self-timed write

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed write cycle.This part supports byte write

operations (see Pin Definitions on page 6 and Truth Table on

page 10 for further details). Write cycles can be one to two or four

bytes wide as controlled by the byte write control inputs. GW

when active LOW causes all bytes to be written.

■ Asynchronous output enable

■ Single cycle chip deselect

■ CY7C1380DV33 is available in JEDEC-standard Pb-free

100-pin TQFP and 165-ball FBGA package and

CY7C1382DV33 is available in 165-ball FBGA package

The CY7C1380DV33/CY7C1382DV33 operates from a +3.3 V

core power supply while all outputs operate with a +2.5 or +3.3 V

power supply. All inputs and outputs are JEDEC-standard and

JESD8-5-compatible.

■ IEEE 1149.1 JTAG-Compatible Boundary Scan

■ ZZ sleep mode option

For a complete list of related documentation, click here.

Selection Guide

Description

Maximum Access Time

200 MHz

3.0

167 MHz Unit

3.4

275

Maximum Operating Current

300

Maximum CMOS Standby Current

Note

1. CE CE are for 100-pin TQFP and 165-ball FBGA packages only.

Cypress Semiconductor Corporation

Document Number: 001-74445 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

December 29, 2015

12 3 4 5 6 7...33

中文翻译

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与CY7C1382DV33相关器件

型号	品牌	获取价格	描述	数据表
CY7C1382DV33-200BZI	CYPRESS	获取价格	18-Mbit (512 K Ã 36/1 M Ã 18) Pipelined SRA
CY7C1382F	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382F-167AXI	CYPRESS	获取价格	Cache SRAM, 1MX18, 3.4ns, CMOS, PQFP100, 20 X 14 MM, 1.4 MM HEIGHT, LEAD FREE, PLASTIC, MS
CY7C1382F-167BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382F-167BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382F-167BGXC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382F-167BGXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382F-200BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382F-200BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382F-200BGXC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM

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