Datasheet > 存储 > SRAM> CY7C1382F-250BZXI

CY7C1382F-250BZXI

更新时间： 2024-09-25 13:01:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
30页	1186K
描述
Cache SRAM, 1MX18, 2.6ns, CMOS, PBGA165, 15 X 13 MM, 1.4 MM HEIGHT, LEAD FREE, MO-216, FBGA-165

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技术参数
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CY7C1382F-250BZXI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LBGA, BGA165,11X15,40
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.84	最长访问时间：	2.6 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	250 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e1	长度：	15 mm
内存密度：	18874368 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	18	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	1048576 words	字数代码：	1000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	1MX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大待机电流：	0.07 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.35 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	13 mm	Base Number Matches：	1

CY7C1382F-250BZXI 数据手册

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CY7C1380D, CY7C1380F

CY7C1382D, CY7C1382F

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Features

Functional Description ^[1]

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200, and 167 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

The

CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F

SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM

cells with advanced synchronous peripheral circuitry and a

two-bit counter for internal burst operation. All synchronous

inputs are gated by registers controlled by a positive edge

triggered clock input (CLK). The synchronous inputs include

all addresses, all data inputs, address-pipelining chip enable

(CE₁), depth-expansion chip enables (CE₂and CE₃^[2]), burst

control inputs (ADSC, ADSP, and ADV), write enables (BW_X,

and BWE), and global write (GW). Asynchronous inputs

include the output enable (OE) and the ZZ pin.

• 2.5V or 3.3V IO power supply

• Fast clock-to-output times

— 2.6 ns (for 250 MHz device)

• Provides high-performance 3-1-1-1 access rate

• User selectable burst counter supporting Intel^®Pentium^®

interleaved or linear burst sequences

Addresses and chip enables are registered at rising edge of

clock when address strobe processor (ADSP) or address

strobe controller (ADSC) are active. Subsequent burst

addresses can be internally generated as they are controlled

by the advance pin (ADV).

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed write cycle.This part supports byte write

operations (see Pin Definitions on page 6 and Truth Table ^[4,

^{5, 6, 7, 8]}on page 9 for further details). Write cycles can be one

to two or four bytes wide as controlled by the byte write control

inputs. GW when active LOW causes all bytes to be written.

• Single cycle chip deselect

• CY7C1380D/CY7C1382D available in JEDEC-standard

Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball

FBGA package. CY7C1380F/CY7C1382F available in

Pb-free and non Pb-free 119-ball BGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• ZZ sleep mode option

The

CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F

operates from a +3.3V core power supply while all outputs

operate with a +2.5 or +3.3V power supply. All inputs and

outputs are JEDEC-standard and JESD8-5-compatible.

Selection Guide

250 MHz

200 MHz

3.0

167 MHz

3.4

Unit

Maximum Access Time

2.6

350

Maximum Operating Current

Maximum CMOS Standby Current

300

275

Notes:

1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2. CE CE are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.

Cypress Semiconductor Corporation

Document #: 38-05543 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised Feburary 07, 2007

12 3 4 5 6 7...30

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与CY7C1382F-250BZXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1382FV25	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-167BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-167BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-167BGXC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-167BGXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-200BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-200BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-200BGXC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-200BGXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-250BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM

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