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CY7C1382F-167AXI

更新时间： 2024-09-25 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
30页 1186K
描述
Cache SRAM, 1MX18, 3.4ns, CMOS, PQFP100, 20 X 14 MM, 1.4 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100

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CY7C1382F-167AXI 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP, QFP100,.63X.87
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.84Is Samacsys：N
最长访问时间：3.4 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：167 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e3
长度：22 mm内存密度：18874368 bit
内存集成电路类型：CACHE SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：100字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.07 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.275 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：16 mm
Base Number Matches：1

CY7C1382F-167AXI 数据手册

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CY7C1380D, CY7C1380F  
CY7C1382D, CY7C1382F  
18-Mbit (512K x 36/1M x 18) Pipelined SRAM  
Features  
Functional Description [1]  
• Supports bus operation up to 250 MHz  
• Available speed grades are 250, 200, and 167 MHz  
• Registered inputs and outputs for pipelined operation  
• 3.3V core power supply  
The  
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F  
SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM  
cells with advanced synchronous peripheral circuitry and a  
two-bit counter for internal burst operation. All synchronous  
inputs are gated by registers controlled by a positive edge  
triggered clock input (CLK). The synchronous inputs include  
all addresses, all data inputs, address-pipelining chip enable  
(CE1), depth-expansion chip enables (CE2 and CE3 [2]), burst  
control inputs (ADSC, ADSP, and ADV), write enables (BWX,  
and BWE), and global write (GW). Asynchronous inputs  
include the output enable (OE) and the ZZ pin.  
• 2.5V or 3.3V IO power supply  
• Fast clock-to-output times  
— 2.6 ns (for 250 MHz device)  
• Provides high-performance 3-1-1-1 access rate  
• User selectable burst counter supporting Intel® Pentium®  
interleaved or linear burst sequences  
Addresses and chip enables are registered at rising edge of  
clock when address strobe processor (ADSP) or address  
strobe controller (ADSC) are active. Subsequent burst  
addresses can be internally generated as they are controlled  
by the advance pin (ADV).  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
• Asynchronous output enable  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed write cycle.This part supports byte write  
operations (see Pin Definitions on page 6 and Truth Table [4,  
5, 6, 7, 8] on page 9 for further details). Write cycles can be one  
to two or four bytes wide as controlled by the byte write control  
inputs. GW when active LOW causes all bytes to be written.  
• Single cycle chip deselect  
• CY7C1380D/CY7C1382D available in JEDEC-standard  
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball  
FBGA package. CY7C1380F/CY7C1382F available in  
Pb-free and non Pb-free 119-ball BGA package  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• ZZ sleep mode option  
The  
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F  
operates from a +3.3V core power supply while all outputs  
operate with a +2.5 or +3.3V power supply. All inputs and  
outputs are JEDEC-standard and JESD8-5-compatible.  
Selection Guide  
250 MHz  
200 MHz  
3.0  
167 MHz  
3.4  
Unit  
ns  
Maximum Access Time  
2.6  
350  
70  
Maximum Operating Current  
Maximum CMOS Standby Current  
300  
275  
mA  
mA  
70  
70  
Notes:  
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.  
2. CE CE are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.  
3,  
2
Cypress Semiconductor Corporation  
Document #: 38-05543 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised Feburary 07, 2007  
1234567...30

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