Datasheet > CY7C1382FV25

CY7C1382FV25

更新时间： 2024-09-25 05:19:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	1156K
描述
18-Mbit (512K x 36/1M x 18) Pipelined SRAM

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CY7C1382FV25 数据手册

CY7C1380DV25, CY7C1380FV25

CY7C1382DV25, CY7C1382FV25

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Features

Functional Description ^[1]

• Supports bus operation up to 250 MHz

The

CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/

CY7C1382FV25 SRAM integrates 512K x 36 and 1M x 18

SRAM cells with advanced synchronous peripheral circuitry

and a two-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a

positive edge triggered clock input (CLK). The synchronous

inputs include all addresses, all data inputs, address-pipelining

chip enable (CE₁), depth expansion chip enables (CE₂and

CE₃^[2]), burst control inputs (ADSC, ADSP, and ADV), write

enables (BW_X, and BWE), and global write (GW).

Asynchronous inputs include the output enable (OE) and the

ZZ pin.

• Available speed grades are 250, 200, and 167 MHz

• Registered inputs and outputs for pipelined operation

• 2.5V core power supply

• Fast clock-to-output times, 2.6 ns (for 250-MHz device)

• Provides high-performance 3-1-1-1 access rate

• User selectable burst counter supporting Intel^®Pentium^®

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self timed writes

Addresses and chip enables are registered at rising edge of

clock when either address strobe processor (ADSP) or

address strobe controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the advance pin (ADV).

• Asynchronous output enable

• Single Cycle Chip Deselect

• CY7C1380DV25/CY7C1382DV25 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non

Pb-free 165-ball FBGA package.

CY7C1380FV25/CY7C1382FV25 available in Pb-free and

non Pb-free 119-ball BGA package

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle.This part supports byte write

operations (see Pin Definitions on page 6 and Truth Table ^[4,

^{5, 6, 7, 8]}on page 9 for further details). Write cycles can be one

to two or four bytes wide as controlled by the byte write control

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• ZZ sleep mode option

inputs. GW when active

causes all bytes to be written.

LOW

The

CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/

CY7C1382FV25 operates from a +2.5V core power supply

while all outputs may operate with a +2.5 supply. All inputs and

outputs are JEDEC-standard and JESD8-5-compatible.

Selection Guide

250 MHz

200 MHz

3.0

167 MHz

3.4

Unit

Maximum Access Time

2.6

350

Maximum Operating Current

Maximum CMOS Standby Current

300

275

Notes:

1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2. CE , CE are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable

Cypress Semiconductor Corporation

Document #: 38-05546 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised Feburary 15, 2007

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与CY7C1382FV25相关器件

型号	品牌	获取价格	描述	数据表
CY7C1382FV25-167BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-167BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-167BGXC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-167BGXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-200BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-200BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-200BGXC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-200BGXI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-250BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM
CY7C1382FV25-250BGI	CYPRESS	获取价格	18-Mbit (512K x 36/1M x 18) Pipelined SRAM

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