CY7C1381A
CY7C1383A
PRELIMINARY
512K x 36 / 1M x 18 Flow-Thru SRAM
isters controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), Burst Control In-
puts (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,
BWc, BWd, and BWe), and Global Write (GW).
Features
• Fast access times: 7.5, 8.5, 9.0, 10.0 ns
• Fast clock speed: 117, 100, 83, 66 MHz
• Provide high-performance 3-1-1-1 access rate
• Optimal for depth expansion
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
• 3.3V (–5% / +10%) power supply
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
• Address, data and control registers
• Internally self-timed Write Cycle
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or address status controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• High-density, high-speed packages
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQ1-DQ8 and DQP1. BWb controls DQ9-DQ16 and
DQP2. BWc controls DQ17-DQ24and DQP3. BWd controls
DQ25-DQ32 and DQP4. BWa, BWb BWc, and BWd can be
active only with BWe being LOW. GW being LOW causes all
bytes to be written. WRITE pass-through capability allows writ-
ten data available at the output for the immediately next READ
cycle. This device also incorporates pipelined enable circuit for
easy depth expansion without penalizing system performance.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
All inputs and outputs of the CY7C1381A and the CY7C1383A
are JEDEC standard JESD8-5 compatible.
The CY7C1381A and CY7C1383A SRAMs integrate
524,288x36 and 1,048,576x18 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for inter-
nal burst operation. All synchronous inputs are gated by reg-
Selection Guide
-117MHz
7.5
-100MHz
8.5
-83MHz
9.0
-66MHz
10.0
180
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
250
230
215
Maximum CMOS Standby Current (mA)
30
30
30
30
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
May 19, 2000
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