Datasheet > 存储 > SRAM> CY7C1366B-225AC

CY7C1366B-225AC

更新时间： 2024-11-15 22:19:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
32页	549K
描述
9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM

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CY7C1366B-225AC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.86
最长访问时间：	2.8 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	225 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	9437184 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	225	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.03 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.25 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD (800)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	14 mm
Base Number Matches：	1

CY7C1366B-225AC 数据手册

CY7C1366B

CY7C1367B

9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM

Features

Functional Description^[1]

• Supports bus operation up to 225 MHz

The CY7C1366B/CY7C1367B SRAM integrates 262,144 x 36

and 524,288 x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

• Available speed grades are 225, 200 and 166 MHz

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

— Depth expansion without wait state

• 3.3V –5% and +10% core power supply (V_DD

• 2.5V / 3.3V I/O operation

address-pipelining Chip Enable (

), depth-expansion Chip

CE₁

)

Enables (CE and

^[2]), Burst Control inputs (

CE₃

ADSC ADSP

), Write Enables (

, and

BW_X

), and Global Write

and

ADV

BWE

(

). Asynchronous inputs include the Output Enable (

)

• Fast clock-to-output times

and the ZZ pin.

— 2.8 ns (for 225-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor ( ) or

ADSP

) are active. Subsequent

Address Strobe Controller (

ADSC

burst addresses can be internally generated as controlled by

the Advance pin ( ).

• Provide high-performance 3-1-1-1 access rate

ADV

• User-selectable burst counter supporting Intel^

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

Pentium^interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

controlled by the byte write control inputs.

active

LOW

This device incorporates an

causes all bytes to be written.

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA

and 165-Ball fBGA packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

The CY7C1366B/CY7C1367B operates from a +3.3V core

power supply while all outputs operate with a +3.3V or a +2.5V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

225 MHz

200 MHz

3.0

166 MHz

3.5

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

2.8

250

220

180

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Notes:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE is for TQFP and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05096 Rev. *B

Revised February 23, 2004

12 3 4 5 6 7...32

中文翻译

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与CY7C1366B-225AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1366B-225AI	CYPRESS	获取价格	9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366B-225BGC	CYPRESS	获取价格	9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366B-225BGI	CYPRESS	获取价格	9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366B-225BZC	CYPRESS	获取价格	9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366B-225BZI	CYPRESS	获取价格	9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366B-250AC	CYPRESS	获取价格	Cache SRAM, 256KX36, 2.6ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1366B-250BGC	CYPRESS	获取价格	Cache SRAM, 256KX36, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CY7C1366B-250BZC	CYPRESS	获取价格	Cache SRAM, 256KX36, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CY7C1366C	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C_06	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM

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