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CY7C1366C-200BGXI PDF预览

CY7C1366C-200BGXI

更新时间： 2024-11-16 05:19:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
29页 544K
描述
9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM

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中文翻译

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CY7C1366C-200BGXI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, BGA-119
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.82最长访问时间：3 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：200 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e1长度：22 mm
内存密度：9437184 bit内存集成电路类型：CACHE SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：119
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA119,7X17,50
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：2.4 mm最大待机电流：0.03 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.22 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：14 mm

CY7C1366C-200BGXI 数据手册

 浏览型号CY7C1366C-200BGXI的Datasheet PDF文件第2页浏览型号CY7C1366C-200BGXI的Datasheet PDF文件第3页浏览型号CY7C1366C-200BGXI的Datasheet PDF文件第4页浏览型号CY7C1366C-200BGXI的Datasheet PDF文件第5页浏览型号CY7C1366C-200BGXI的Datasheet PDF文件第6页浏览型号CY7C1366C-200BGXI的Datasheet PDF文件第7页 
CY7C1366C  
CY7C1367C  
9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM  
Features  
Functional Description[1]  
• Supports bus operation up to 250 MHz  
The CY7C1366C/CY7C1367C SRAM integrates 256K x 36  
and 512K x 18 SRAM cells with advanced synchronous  
peripheral circuitry and a two-bit counter for internal burst  
operation. All synchronous inputs are gated by registers  
controlled by a positive-edge-triggered Clock Input (CLK). The  
synchronous inputs include all addresses, all data inputs,  
address-pipelining Chip Enable (CE1), depth-expansion Chip  
Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP,  
• Available speed grades are 250, 200, and 166 MHz  
• Registered inputs and outputs for pipelined operation  
• Optimal for performance (Double-Cycle deselect)  
—Depth expansion without wait state  
• 3.3V –5% and +10% core power supply (VDD  
)
• 2.5 V/3.3V I/O power supply (VDDQ  
)
ADV), Write Enables (BW , and BWE), and Global Write  
and  
X
(GW). Asynchronous inputs include the Output Enable (OE)  
and the ZZ pin.  
• Fast clock-to-output times  
— 2.8 ns (for 250-MHz device)  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
• Provide high-performance 3-1-1-1 access rate  
• User-selectable burst counter supporting Intel®  
Pentium® interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to four bytes wide as  
• Asynchronous output enable  
• Available in lead-Free 100-Pin TQFP, lead-free and non  
lead-free 119-Ball BGA package and 165-Ball FBGA  
package  
controlled by the byte write control inputs. GW  
active  
LOW  
This device incorporates an  
causes all bytes to be written.  
additional pipelined enable register which delays turning off  
the output buffers an additional cycle when a deselect is  
executed.This feature allows depth expansion without penal-  
izing system performance.  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode Option  
The CY7C1366C/CY7C1367C operates from a +3.3V core  
power supply while all outputs operate with a +3.3V or a +2.5V  
supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
250 MHz  
200 MHz  
3.0  
166 MHz  
3.5  
Unit  
ns  
Maximum Access Time  
2.8  
250  
40  
Maximum Operating Current  
Maximum CMOS Standby Current  
220  
180  
mA  
mA  
40  
40  
Notes:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE is for TQFP and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.  
3
Cypress Semiconductor Corporation  
Document #: 38-05542 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 14, 2006  
[+] Feedback  
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