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CY7C1366B-250BGC PDF预览

CY7C1366B-250BGC

更新时间： 2024-11-16 20:48:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
27页 637K
描述
Cache SRAM, 256KX36, 2.6ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

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CY7C1366B-250BGC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.86最长访问时间：2.6 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：250 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
长度：22 mm内存密度：9437184 bit
内存集成电路类型：CACHE SRAM内存宽度：36
湿度敏感等级：1功能数量：1
端子数量：119字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：225电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：2.4 mm
最大待机电流：0.03 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.25 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

CY7C1366B-250BGC 数据手册

 浏览型号CY7C1366B-250BGC的Datasheet PDF文件第2页浏览型号CY7C1366B-250BGC的Datasheet PDF文件第3页浏览型号CY7C1366B-250BGC的Datasheet PDF文件第4页浏览型号CY7C1366B-250BGC的Datasheet PDF文件第5页浏览型号CY7C1366B-250BGC的Datasheet PDF文件第6页浏览型号CY7C1366B-250BGC的Datasheet PDF文件第7页 
CY7C1366B  
CY7C1367B  
PRELIMINARY  
256K x 36/512K x 18 Pipelined  
Double-cycle Deselect SRAM  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock.  
Maximum access delay from the clock rise is 2.6 ns (250 MHz  
device).  
Features  
• Supports bus operation up to 250 MHz  
— Available speed grades are 250, 200, and 166 MHz  
• Fully registered inputs and outputs for pipelined  
operation  
• Single 3.3V power supply  
• Supports 3.3V and 2.5V I/Os  
• Fast clock-to-output times  
— 2.6ns (for 250 MHz device)  
The CY7C1366B and CY7C1367B support either the inter-  
leaved burst sequence used by the Intel Pentium processor or  
a linear burst sequence used by processors such as the  
PowerPC™. The burst sequence is selected through the  
MODE pin (Pin 31 and ball R3 for the TQFP and BGA  
packages, respectively.) Accesses can be initiated by  
asserting either the Processor Address Strobe (ADSP) or the  
Controller Address Strobe (ADSC) at clock rise. Address  
advancement through the burst sequence is controlled by the  
ADV input. A 2-bit on-chip wraparound burst counter captures  
the first address in a burst sequence and automatically incre-  
ments the address for the rest of the burst access.  
— 3.0ns (for 200 MHz device)  
— 3.5 ns (for 166 MHz device)  
• User-selectable burst counter supporting Intel  
Pentium® interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
• Two Cycle Chip Deselect  
• Available as a 100-pin TQFP, 119-Ball BGA, 165-Ball  
FBGA  
Byte write operations are qualified with the Byte Write Select  
(BWa,b,c,d for 1366B and BWa,b for 1367B) inputs. A Global  
Write Enable (GW) overrides all byte write inputs and writes  
data to all four bytes. All writes are conducted with on-chip  
synchronous self-timed write circuitry.  
Three synchronous Chip Selects (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output three-state control. In order to provide  
proper data during depth expansion, OE is masked during the  
first clock of a read cycle when emerging from a deselected  
state.  
• TQFP and FBGA has 3 Chip Enables  
• 119 BGA has 2-Chip Enables  
• IEEE 1149.1 JTAG-compatible Boundary Scan for 119  
BGA and 165 FBGA Packages  
• “ZZ” Sleep Mode option and Stop Clock option  
Functional Description  
The CY7C1366B and CY7C1367B are 3.3V, 256K x 36 and  
512K x 18 synchronous-pipelined cache SRAM, respectively.  
Logic Block Diagram  
D
CLK  
Data-In REG.  
CE  
Q
ADV  
1366B  
1367B  
A
x
A
A
A
[17:0]  
[18:0]  
X
GW  
CE  
CE  
CE  
CONTROL  
and WRITE  
LOGIC  
256Kx36/  
512Kx18  
DQ  
DQ  
a,b  
a,b,c,d  
DQ  
1
2
X
DQP  
BW  
DQP  
DQP  
DQ  
DQP  
a,b,c,d  
a,b  
X
x
x
MEMORY  
ARRAY  
3
BW  
BW  
a,b,c,d  
a,b  
BWE  
X
BW  
x
MODE  
ADSP  
ADSC  
ZZ  
OE  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05096 Rev. *A  
Revised November 12, 2002  
1234567...27

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CY7C1366C-166AXI CYPRESS

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 		Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC,
CY7C1366C-166BGC CYPRESS

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 		9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-166BGCT CYPRESS

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 		SRAM,

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