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CY7C1366C-166BZI PDF预览

CY7C1366C-166BZI

更新时间: 2024-11-15 23:13:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
27页 457K
描述
9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM

CY7C1366C-166BZI 数据手册

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CY7C1366C  
CY7C1367C  
PRELIMINARY  
9-Mbit (256K x 36/512K x 18) Pipelined DCD  
Sync SRAM  
Features  
Functional Description[1]  
• Supports bus operation up to 225 MHz  
The CY7C1366C/CY7C1367C SRAM integrates 262,144 x 36  
and 524,288 x 18 SRAM cells with advanced synchronous  
peripheral circuitry and a two-bit counter for internal burst  
operation. All synchronous inputs are gated by registers  
controlled by a positive-edge-triggered Clock Input (CLK). The  
synchronous inputs include all addresses, all data inputs,  
• Available speed grades are 225, 200 and 166 MHz  
• Registered inputs and outputs for pipelined operation  
•Optimal for performance (Double-Cycle deselect)  
—Depth expansion without wait state  
•3.3V –5% and +10% core power supply (VDD  
• 2.5V / 3.3V I/O operation  
address-pipelining Chip Enable (  
), depth-expansion Chip  
CE1  
)
Enables (CE and  
[2]), Burst Control inputs (  
,
,
CE3  
2
ADSC ADSP  
), Write Enables (  
, and  
BWX  
), and Global Write  
and  
ADV  
BWE  
(
). Asynchronous inputs include the Output Enable (  
GW  
)
OE  
• Fast clock-to-output times  
and the ZZ pin.  
— 2.8 ns (for 225-MHz device)  
— 3.0 ns (for 200-MHz device)  
— 3.5 ns (for 166-MHz device)  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor ( ) or  
ADSP  
) are active. Subsequent  
Address Strobe Controller (  
ADSC  
burst addresses can be internally generated as controlled by  
the Advance pin ( ).  
• Provide high-performance 3-1-1-1 access rate  
ADV  
User-selectable burst counter supporting Intel  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to four bytes wide as  
Pentiuminterleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
controlled by the byte write control inputs.  
active  
GW  
LOW  
This device incorporates an  
causes all bytes to be written.  
additional pipelined enable register which delays turning off  
the output buffers an additional cycle when a deselect is  
executed.This feature allows depth expansion without penal-  
izing system performance.  
• AvailableinLead-Free100TQFP,119BGAand165fBGA  
packages  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
• “ZZ” Sleep Mode Option  
The CY7C1366C/CY7C1367C operates from a +3.3V core  
power supply while all outputs operate with a +3.3V or a +2.5V  
supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
225 MHz  
200 MHz  
3.0  
166 MHz  
3.5  
Unit  
ns  
mA  
mA  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
2.8  
250  
30  
220  
30  
180  
30  
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.  
Notes:  
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE is for TQFP and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.  
3
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-05542 Rev. *A  
Revised October 5, 2004  

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