Datasheet > 存储 > SRAM> CY7C1366C-166BGXI

CY7C1366C-166BGXI

更新时间： 2024-09-29 05:19:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	544K
描述
9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1366C-166BGXI 数据手册

浏览型号CY7C1366C-166BGXI的Datasheet PDF文件第2页

浏览型号CY7C1366C-166BGXI的Datasheet PDF文件第3页

浏览型号CY7C1366C-166BGXI的Datasheet PDF文件第4页

浏览型号CY7C1366C-166BGXI的Datasheet PDF文件第5页

浏览型号CY7C1366C-166BGXI的Datasheet PDF文件第6页

CY7C1366C

CY7C1367C

9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

The CY7C1366C/CY7C1367C SRAM integrates 256K x 36

and 512K x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE₁), depth-expansion Chip

Enables (CE₂and CE₃^[2]), Burst Control inputs (ADSC, ADSP,

• Available speed grades are 250, 200, and 166 MHz

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

—Depth expansion without wait state

• 3.3V –5% and +10% core power supply (V_DD

)

• 2.5 V/3.3V I/O power supply (V_DDQ

)

ADV), Write Enables (BW , and BWE), and Global Write

and

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

• Fast clock-to-output times

— 2.8 ns (for 250-MHz device)

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

• Asynchronous output enable

• Available in lead-Free 100-Pin TQFP, lead-free and non

lead-free 119-Ball BGA package and 165-Ball FBGA

package

controlled by the byte write control inputs. GW

active

LOW

This device incorporates an

causes all bytes to be written.

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

The CY7C1366C/CY7C1367C operates from a +3.3V core

power supply while all outputs operate with a +3.3V or a +2.5V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

250 MHz

200 MHz

3.0

166 MHz

3.5

Unit

Maximum Access Time

2.8

250

Maximum Operating Current

Maximum CMOS Standby Current

220

180

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE is for TQFP and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.

Cypress Semiconductor Corporation

Document #: 38-05542 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 14, 2006

[+] Feedback

12 3 4 5 6 7...29

中文翻译

下载PDF

与CY7C1366C-166BGXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1366C-166BZC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-166BZI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-166BZXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-166BZXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-200AXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-200AXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-200BGC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-200BGI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-200BGXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-200BGXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM

与CY7C1366C-166BGXI相关文章

塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

25
英特尔震撼发布：128核心256线程的至强6性能核处理器
2024-09-29

22
SK海力士量产12层HBM3E，容量高达36GB
2024-09-27

22
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
2024-09-27

34

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1366C-166BGXI

CY7C1366C-166BGXI 数据手册

与CY7C1366C-166BGXI相关器件

与CY7C1366C-166BGXI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1366C-166BGXI

CY7C1366C-166BGXI 数据手册

与CY7C1366C-166BGXI相关器件

与CY7C1366C-166BGXI相关文章

您还可以找

您在本页遇到什么问题？