Datasheet > 存储 > SRAM> CY7C1366C-250AXI

CY7C1366C-250AXI

更新时间： 2024-11-16 05:19:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
29页	544K
描述
9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM

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CY7C1366C-250AXI 数据手册

CY7C1366C

CY7C1367C

9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM

Features

Functional Description^[1]

• Supports bus operation up to 250 MHz

The CY7C1366C/CY7C1367C SRAM integrates 256K x 36

and 512K x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE₁), depth-expansion Chip

Enables (CE₂and CE₃^[2]), Burst Control inputs (ADSC, ADSP,

• Available speed grades are 250, 200, and 166 MHz

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

—Depth expansion without wait state

• 3.3V –5% and +10% core power supply (V_DD

)

• 2.5 V/3.3V I/O power supply (V_DDQ

)

ADV), Write Enables (BW , and BWE), and Global Write

and

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

• Fast clock-to-output times

— 2.8 ns (for 250-MHz device)

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^®

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

• Asynchronous output enable

• Available in lead-Free 100-Pin TQFP, lead-free and non

lead-free 119-Ball BGA package and 165-Ball FBGA

package

controlled by the byte write control inputs. GW

active

LOW

This device incorporates an

causes all bytes to be written.

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

The CY7C1366C/CY7C1367C operates from a +3.3V core

power supply while all outputs operate with a +3.3V or a +2.5V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

250 MHz

200 MHz

3.0

166 MHz

3.5

Unit

Maximum Access Time

2.8

250

Maximum Operating Current

Maximum CMOS Standby Current

220

180

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE is for TQFP and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.

Cypress Semiconductor Corporation

Document #: 38-05542 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 14, 2006

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与CY7C1366C-250AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1366C-250BGC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-250BGI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-250BGXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-250BGXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-250BZC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-250BZI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-250BZXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-250BZXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1367A	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM
CY7C1367A-150AC	CYPRESS	获取价格	256K x 36/512K x 18 Pipelined SRAM

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