Datasheet > CY7C1366B-250BZC

CY7C1366B-250BZC

更新时间： 2024-11-16 20:48:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟静态存储器内存集成电路
页数	文件大小	规格书
27页	637K
描述
Cache SRAM, 256KX36, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165

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CY7C1366B-250BZC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.86	最长访问时间：	2.6 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	250 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
长度：	15 mm	内存密度：	9437184 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	36
湿度敏感等级：	1	功能数量：	1
端子数量：	165	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	225	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大待机电流：	0.03 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.25 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	13 mm	Base Number Matches：	1

CY7C1366B-250BZC 数据手册

CY7C1366B

CY7C1367B

PRELIMINARY

256K x 36/512K x 18 Pipelined

Double-cycle Deselect SRAM

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

Maximum access delay from the clock rise is 2.6 ns (250 MHz

device).

Features

• Supports bus operation up to 250 MHz

— Available speed grades are 250, 200, and 166 MHz

• Fully registered inputs and outputs for pipelined

operation

• Single 3.3V power supply

• Supports 3.3V and 2.5V I/Os

• Fast clock-to-output times

— 2.6ns (for 250 MHz device)

The CY7C1366B and CY7C1367B support either the inter-

leaved burst sequence used by the Intel Pentium processor or

a linear burst sequence used by processors such as the

PowerPC™. The burst sequence is selected through the

MODE pin (Pin 31 and ball R3 for the TQFP and BGA

packages, respectively.) Accesses can be initiated by

asserting either the Processor Address Strobe (ADSP) or the

Controller Address Strobe (ADSC) at clock rise. Address

advancement through the burst sequence is controlled by the

ADV input. A 2-bit on-chip wraparound burst counter captures

the first address in a burst sequence and automatically incre-

ments the address for the rest of the burst access.

— 3.0ns (for 200 MHz device)

— 3.5 ns (for 166 MHz device)

• User-selectable burst counter supporting Intel

Pentium^®interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Two Cycle Chip Deselect

• Available as a 100-pin TQFP, 119-Ball BGA, 165-Ball

FBGA

Byte write operations are qualified with the Byte Write Select

(BW_a,b,c,dfor 1366B and BW_a,bfor 1367B) inputs. A Global

Write Enable (GW) overrides all byte write inputs and writes

data to all four bytes. All writes are conducted with on-chip

synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to provide

proper data during depth expansion, OE is masked during the

first clock of a read cycle when emerging from a deselected

state.

• TQFP and FBGA has 3 Chip Enables

• 119 BGA has 2-Chip Enables

• IEEE 1149.1 JTAG-compatible Boundary Scan for 119

BGA and 165 FBGA Packages

• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

The CY7C1366B and CY7C1367B are 3.3V, 256K x 36 and

512K x 18 synchronous-pipelined cache SRAM, respectively.

Logic Block Diagram

CLK

Data-In REG.

ADV

1366B

1367B

[17:0]

[18:0]

CONTROL

and WRITE

LOGIC

256Kx36/

512Kx18

a,b

a,b,c,d

DQP

a,b,c,d

a,b

MEMORY

ARRAY

a,b,c,d

a,b

BWE

MODE

ADSP

ADSC

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05096 Rev. *A

Revised November 12, 2002

12 3 4 5 6 7...27

中文翻译

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与CY7C1366B-250BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1366C	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C_06	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C_12	CYPRESS	获取价格	9-Mbit (256 K Ã 36/512 K Ã 18) Pipelined DC
CY7C1366C-166AXC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-166AXCT	CYPRESS	获取价格	SRAM,
CY7C1366C-166AXI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-166AXIT	CYPRESS	获取价格	Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC,
CY7C1366C-166BGC	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366C-166BGCT	CYPRESS	获取价格	SRAM,
CY7C1366C-166BGI	CYPRESS	获取价格	9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM

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