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CY7C1347F-166AI PDF预览

CY7C1347F-166AI

更新时间： 2024-11-24 22:15:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
19页 423K
描述
4-Mbit (128K x 36) Pipelined Sync SRAM

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CY7C1347F-166AI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP, QFP100,.63X.87
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.88最长访问时间：3.5 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：166 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：4718592 bit内存集成电路类型：CACHE SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：100
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：225
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.01 A
最小待机电流：3.13 V子类别：SRAMs
最大压摆率：0.24 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD (800)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mm

CY7C1347F-166AI 数据手册

 浏览型号CY7C1347F-166AI的Datasheet PDF文件第2页浏览型号CY7C1347F-166AI的Datasheet PDF文件第3页浏览型号CY7C1347F-166AI的Datasheet PDF文件第4页浏览型号CY7C1347F-166AI的Datasheet PDF文件第5页浏览型号CY7C1347F-166AI的Datasheet PDF文件第6页浏览型号CY7C1347F-166AI的Datasheet PDF文件第7页 
CY7C1347F  
4-Mbit (128K x 36) Pipelined Sync SRAM  
Features  
Functional Description[1]  
The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined  
SRAM designed to support zero-wait-state secondary cache  
with minimal glue logic.  
• Fully registered inputs and outputs for pipelined oper-  
ation  
• 128K by 36 common I/O architecture  
• 3.3V core power supply  
• 2.5V/3.3V I/O operation  
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
— 2.6 ns (for 225-MHz device)  
— 2.8 ns (for 200-MHz device)  
— 3.5 ns (for 166-MHz device)  
— 4.0 ns (for 133-MHz device)  
CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V  
level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V.  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock.  
Maximum access delay from the clock rise is 2.6 ns (250-MHz  
device)  
CY7C1347F supports either the interleaved burst sequence  
used by the Intel Pentium processor or a linear burst sequence  
used by processors such as the PowerPC®. The burst  
sequence is selected through the MODE pin. Accesses can be  
initiated by asserting either the Address Strobe from  
Processor (ADSP) or the Address Strobe from Controller  
(ADSC) at clock rise. Address advancement through the burst  
sequence is controlled by the ADV input. A 2-bit on-chip  
wraparound burst counter captures the first address in a burst  
sequence and automatically increments the address for the  
rest of the burst access.  
• User-selectable burst counter supporting Intel  
Pentiuminterleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
• JEDEC-standard 100-pin TQFP, 119-pin BGA and  
165-pin fBGA packages  
Byte write operations are qualified with the four Byte Write  
Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides  
all byte write inputs and writes data to all four bytes. All writes  
are conducted with on-chip synchronous self-timed write  
circuitry.  
• “ZZ” Sleep Mode option and Stop Clock option  
• Available in Industrial and Commercial temperature  
ranges  
Three synchronous Chip Selects (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output three-state control. In order to provide  
proper data during depth expansion, OE is masked during the  
first clock of a read cycle when emerging from a deselected  
state.  
Logic Block Diagram  
A0, A1, A  
ADDRESS  
REGISTER  
2
A[1:0]  
MODE  
Q1  
ADV  
CLK  
BURST  
COUNTER  
AND  
CLR  
Q0  
LOGIC  
ADSC  
ADSP  
DQ  
BYTE  
WRITE REGISTER  
D ,DQPD  
DQ  
BYTE  
WRITE DRIVER  
D ,DQPD  
BWD  
DQC ,DQP  
BYTE  
WRITE DRIVER  
C
DQC ,DQP  
BYTE  
WRITE REGISTER  
C
BW  
C
OUTPUT  
BUFFERS  
OUTPUT  
REGISTERS  
MEMORY  
ARRAY  
DQ s  
SENSE  
AMPS  
DQP  
DQP  
DQP  
A
DQB ,DQP  
BYTE  
WRITE DRIVER  
B
E
DQB ,DQP  
BYTE  
WRITE REGISTER  
B
B
C
BW  
B
DQPD  
DQ  
BYTE  
WRITE DRIVER  
A ,DQPA  
DQ  
BYTE  
WRITE REGISTER  
A ,DQPA  
BWA  
BWE  
INPUT  
REGISTERS  
GW  
ENABLE  
REGISTER  
PIPELINED  
ENABLE  
CE  
CE  
CE  
1
2
3
OE  
SLEEP  
CONTROL  
ZZ  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05213 Rev. *D  
Revised April 9, 2004  
1234567...19

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