Datasheet > CY7C1347G_13

CY7C1347G_13

更新时间： 2024-11-27 12:27:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
26页	567K
描述
4-Mbit (128 K x 36) Pipelined Sync SRAM

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CY7C1347G_13 数据手册

CY7C1347G

4-Mbit (128 K × 36) Pipelined Sync SRAM

4-Mbit (128

K × 36) Pipelined Sync SRAM

Features

Functional Description

The CY7C1347G is a 3.3 V, 128 K × 36 synchronous pipelined

■ Fully registered inputs and outputs for pipelined operation

■ 128 K × 36 common I/O architecture

SRAM designed to support zero-wait-state secondary cache

with minimal glue logic. CY7C1347G I/O pins can operate at

either the 2.5 V or the 3.3 V level. The I/O pins are 3.3 V tolerant

when V_DDQ= 2.5 V. All synchronous inputs pass through input

registers controlled by the rising edge of the clock. All data

outputs pass through output registers controlled by the rising

edge of the clock. Maximum access delay from the clock rise is

2.6 ns (250 MHz device). CY7C1347G supports either the

interleaved burst sequence used by the Intel Pentium processor

or a linear burst sequence used by processors such as the

PowerPC. The burst sequence is selected through the MODE

pin. Accesses can be initiated by asserting either the address

strobe from processor (ADSP) or the address strobe from

controller (ADSC) at clock rise. Address advancement through

the burst sequence is controlled by the ADV input. A 2-bit on-chip

wraparound burst counter captures the first address in a burst

sequence and automatically increments the address for the rest

of the burst access.

■ 3.3 V core power supply (V_DD

)

■ 2.5- / 3.3-V I/O power supply (V_DDQ

)

■ Fast clock to output times: 2.6 ns (for 250 MHz device)

■ User selectable burst counter supporting Intel Pentium

interleaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self timed writes

■ Asynchronous output enable

■ Offered in Pb-free 100-pin TQFP, Pb-free 119-ball BGA

package

■ “ZZ” sleep mode option and stop clock option

■ Available in commercial temperature range

Byte write operations are qualified with the four Byte Write Select

(BW_[A:D]) inputs. A global write enable (GW) overrides all byte

write inputs and writes data to all four bytes. All writes are

conducted with on-chip synchronous self timed write circuitry.

Three synchronous chip Selects (CE₁, CE₂, CE₃) and an

asynchronous output enable (OE) provide for easy bank

selection and output tristate control. To provide proper data

during depth expansion, OE is masked during the first clock of a

read cycle when emerging from a deselected state.

Selection Guide

Description

Maximum access time

250 MHz 200 MHz

166 MHz

3.5

133 MHz Unit

2.6

325

2.8

265

4.0

225

Maximum operating current

240

Maximum CMOS standby current

Errata: For information on silicon errata, see "Errata" on page 23. Details include trigger conditions, devices affected, and proposed workaround.

Cypress Semiconductor Corporation

Document Number: 38-05516 Rev. *N

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 25, 2013

12 3 4 5 6 7...26

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与CY7C1347G_13相关器件

型号	品牌	获取价格	描述	数据表
CY7C1347G-133AXC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133AXCT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-
CY7C1347G-133AXI	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133BGC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133BGI	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133BGXC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133BGXI	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133BZC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133BZI	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133BZXC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined Sync SRAM

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