5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> CY7C1347G-133AXC
CY7C1347G-133AXC PDF预览

CY7C1347G-133AXC

更新时间： 2024-11-27 03:01:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
21页 1019K
描述
4-Mbit (128K x 36) Pipelined Sync SRAM

阅读下载

中文翻译

获取价格

CY7C1347G-133AXC 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP, QFP100,.63X.87针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41Factory Lead Time：1 week
风险等级：5.69Is Samacsys：N
最长访问时间：4 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：133 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e3
长度：20 mm内存密度：4718592 bit
内存集成电路类型：CACHE SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：100字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：128KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.04 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.225 mA
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：14 mm
Base Number Matches：1

CY7C1347G-133AXC 数据手册

 浏览型号CY7C1347G-133AXC的Datasheet PDF文件第2页浏览型号CY7C1347G-133AXC的Datasheet PDF文件第3页浏览型号CY7C1347G-133AXC的Datasheet PDF文件第4页浏览型号CY7C1347G-133AXC的Datasheet PDF文件第5页浏览型号CY7C1347G-133AXC的Datasheet PDF文件第6页浏览型号CY7C1347G-133AXC的Datasheet PDF文件第7页 
CY7C1347G  
4-Mbit (128K x 36) Pipelined Sync SRAM  
Features  
Functional Description[1]  
The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined  
• Fully registered inputs and outputs for pipelined operation  
• 128K x 36 common IO architecture  
SRAM designed to support zero-wait-state secondary cache  
with minimal glue logic. CY7C1347G IO pins can operate at  
either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant  
when VDDQ = 2.5V. All synchronous inputs pass through input  
registers controlled by the rising edge of the clock. All data  
outputs pass through output registers controlled by the rising  
edge of the clock. Maximum access delay from the clock rise  
is 2.6 ns (250 MHz device). CY7C1347G supports either the  
interleaved burst sequence used by the Intel Pentium  
processor or a linear burst sequence used by processors such  
as the PowerPC®. The burst sequence is selected through the  
MODE pin. Accesses can be initiated by asserting either the  
Address Strobe from Processor (ADSP) or the Address Strobe  
from Controller (ADSC) at clock rise. Address advancement  
through the burst sequence is controlled by the ADV input. A  
2-bit on-chip wraparound burst counter captures the first  
address in a burst sequence and automatically increments the  
address for the rest of the burst access.  
• 3.3V core power supply (VDD  
)
• 2.5V/3.3V I/O power supply (VDDQ  
)
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
• User-selectable burst counter supporting Intel® Pentium®  
interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
• Offered in lead-free 100-Pin TQFP, lead-free and non-  
lead-free 119-Ball BGA package and 165-Ball FBGA  
package  
• “ZZ” sleep mode option and stop clock option  
• Available in industrial and commercial temperature ranges  
Byte write operations are qualified with the four Byte Write  
Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides  
all byte write inputs and writes data to all four bytes. All writes  
are conducted with on-chip synchronous self-timed write  
circuitry.  
Three synchronous Chip Selects (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to provide proper  
data during depth expansion, OE is masked during the first  
clock of a read cycle when emerging from a deselected state.  
Selection Guide  
250 MHz  
200 MHz  
2.8  
166 MHz  
3.5  
133 MHz  
4.0  
Unit  
ns  
Maximum Access Time  
2.6  
325  
40  
Maximum Operating Current  
Maximum CMOS Standby Current  
265  
240  
225  
mA  
mA  
40  
40  
40  
Note  
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.  
Cypress Semiconductor Corporation  
Document #: 38-05516 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised May 22, 2007  
[+] Feedback  
1234567...21

中文翻译

下载PDF

CY7C1347G-133AXC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1347G-133AXCT CYPRESS

类似代替

 ZBT SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-
CY7C1347F-133AC CYPRESS

类似代替

 4-Mbit (128K x 36) Pipelined Sync SRAM

与CY7C1347G-133AXC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1347G-133AXCT CYPRESS

获取价格

 		ZBT SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-
CY7C1347G-133AXI CYPRESS

获取价格

 		4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133BGC CYPRESS

获取价格

 		4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133BGI CYPRESS

获取价格

 		4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133BGXC CYPRESS

获取价格

 		4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133BGXI CYPRESS

获取价格

 		4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133BZC CYPRESS

获取价格

 		4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133BZI CYPRESS

获取价格

 		4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133BZXC CYPRESS

获取价格

 		4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133BZXI CYPRESS

获取价格

 		4-Mbit (128K x 36) Pipelined Sync SRAM

与CY7C1347G-133AXC相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证