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CY7C1347G-133AXCT PDF预览

CY7C1347G-133AXCT

更新时间： 2024-11-25 19:36:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
26页 496K
描述
ZBT SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100

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CY7C1347G-133AXCT 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：LQFP, QFP100,.63X.87Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.81最长访问时间：4 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：133 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：4718592 bit内存集成电路类型：ZBT SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：100
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：128KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.04 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.225 mA
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：14 mmBase Number Matches：1

CY7C1347G-133AXCT 数据手册

 浏览型号CY7C1347G-133AXCT的Datasheet PDF文件第2页浏览型号CY7C1347G-133AXCT的Datasheet PDF文件第3页浏览型号CY7C1347G-133AXCT的Datasheet PDF文件第4页浏览型号CY7C1347G-133AXCT的Datasheet PDF文件第5页浏览型号CY7C1347G-133AXCT的Datasheet PDF文件第6页浏览型号CY7C1347G-133AXCT的Datasheet PDF文件第7页 
CY7C1347G  
4-Mbit (128K × 36) Pipelined Sync SRAM  
4-Mbit (128K  
× 36) Pipelined Sync SRAM  
Features  
Functional Description  
The CY7C1347G is a 3.3 V, 128K × 36 synchronous pipelined  
■ Fully registered inputs and outputs for pipelined operation  
■ 128K × 36 common I/O architecture  
SRAM designed to support zero-wait-state secondary cache  
with minimal glue logic. CY7C1347G I/O pins can operate at  
either the 2.5 V or the 3.3 V level. The I/O pins are 3.3 V tolerant  
when VDDQ = 2.5 V. All synchronous inputs pass through input  
registers controlled by the rising edge of the clock. All data  
outputs pass through output registers controlled by the rising  
edge of the clock. Maximum access delay from the clock rise is  
2.6 ns (250 MHz device). CY7C1347G supports either the  
interleaved burst sequence used by the Intel Pentium processor  
or a linear burst sequence used by processors such as the  
PowerPC. The burst sequence is selected through the MODE  
pin. Accesses can be initiated by asserting either the address  
strobe from processor (ADSP) or the address strobe from  
controller (ADSC) at clock rise. Address advancement through  
the burst sequence is controlled by the ADV input. A 2-bit on-chip  
wraparound burst counter captures the first address in a burst  
sequence and automatically increments the address for the rest  
of the burst access.  
■ 3.3 V core power supply (VDD  
)
■ 2.5 V/ 3.3 V I/O power supply (VDDQ  
)
■ Fast clock to output times: 2.6 ns (for 250 MHz device)  
■ User selectable burst counter supporting IntelPentium  
interleaved or linear burst sequences  
■ Separate processor and controller address strobes  
■ Synchronous self timed writes  
■ Asynchronous output enable  
■ Offered in Pb-free 100-pin TQFP package  
■ “ZZ” sleep mode option and stop clock option  
■ Available in commercial and industrial temperature range  
Byte write operations are qualified with the four Byte Write Select  
(BW[A:D]) inputs. A global write enable (GW) overrides all byte  
write inputs and writes data to all four bytes. All writes are  
conducted with on-chip synchronous self timed write circuitry.  
Three synchronous chip Selects (CE1, CE2, CE3) and an  
asynchronous output enable (OE) provide for easy bank  
selection and output tristate control. To provide proper data  
during depth expansion, OE is masked during the first clock of a  
read cycle when emerging from a deselected state.  
For a complete list of related documentation, click here.  
Selection Guide  
Description  
Maximum access time  
250 MHz 200 MHz  
166 MHz  
3.5  
133 MHz Unit  
2.6  
325  
40  
2.8  
265  
40  
4.0  
225  
40  
ns  
Maximum operating current  
240  
mA  
mA  
Maximum CMOS standby current  
40  
Errata: For information on silicon errata, see "Errata" on page 22. Details include trigger conditions, devices affected, and proposed workaround.  
Cypress Semiconductor Corporation  
Document Number: 38-05516 Rev. *S  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised January 23, 2018  
 
 
 
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CY7C1347G-133AXCT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1347G-133AXC CYPRESS

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