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CY7C1347G-166BZXC PDF预览

CY7C1347G-166BZXC

更新时间： 2024-11-25 03:01:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
21页 1019K
描述
4-Mbit (128K x 36) Pipelined Sync SRAM

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CY7C1347G-166BZXC 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：LBGA, BGA165,11X15,40
针数：165Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.82最长访问时间：3.5 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：166 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B165
JESD-609代码：e1长度：15 mm
内存密度：4718592 bit内存集成电路类型：CACHE SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：165
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：128KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LBGA封装等效代码：BGA165,11X15,40
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.4 mm最大待机电流：0.04 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.24 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：13 mm

CY7C1347G-166BZXC 数据手册

 浏览型号CY7C1347G-166BZXC的Datasheet PDF文件第2页浏览型号CY7C1347G-166BZXC的Datasheet PDF文件第3页浏览型号CY7C1347G-166BZXC的Datasheet PDF文件第4页浏览型号CY7C1347G-166BZXC的Datasheet PDF文件第5页浏览型号CY7C1347G-166BZXC的Datasheet PDF文件第6页浏览型号CY7C1347G-166BZXC的Datasheet PDF文件第7页 
CY7C1347G  
4-Mbit (128K x 36) Pipelined Sync SRAM  
Features  
Functional Description[1]  
The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined  
• Fully registered inputs and outputs for pipelined operation  
• 128K x 36 common IO architecture  
SRAM designed to support zero-wait-state secondary cache  
with minimal glue logic. CY7C1347G IO pins can operate at  
either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant  
when VDDQ = 2.5V. All synchronous inputs pass through input  
registers controlled by the rising edge of the clock. All data  
outputs pass through output registers controlled by the rising  
edge of the clock. Maximum access delay from the clock rise  
is 2.6 ns (250 MHz device). CY7C1347G supports either the  
interleaved burst sequence used by the Intel Pentium  
processor or a linear burst sequence used by processors such  
as the PowerPC®. The burst sequence is selected through the  
MODE pin. Accesses can be initiated by asserting either the  
Address Strobe from Processor (ADSP) or the Address Strobe  
from Controller (ADSC) at clock rise. Address advancement  
through the burst sequence is controlled by the ADV input. A  
2-bit on-chip wraparound burst counter captures the first  
address in a burst sequence and automatically increments the  
address for the rest of the burst access.  
• 3.3V core power supply (VDD  
)
• 2.5V/3.3V I/O power supply (VDDQ  
)
• Fast clock-to-output times  
— 2.6 ns (for 250-MHz device)  
• User-selectable burst counter supporting Intel® Pentium®  
interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
• Offered in lead-free 100-Pin TQFP, lead-free and non-  
lead-free 119-Ball BGA package and 165-Ball FBGA  
package  
• “ZZ” sleep mode option and stop clock option  
• Available in industrial and commercial temperature ranges  
Byte write operations are qualified with the four Byte Write  
Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides  
all byte write inputs and writes data to all four bytes. All writes  
are conducted with on-chip synchronous self-timed write  
circuitry.  
Three synchronous Chip Selects (CE1, CE2, CE3) and an  
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to provide proper  
data during depth expansion, OE is masked during the first  
clock of a read cycle when emerging from a deselected state.  
Selection Guide  
250 MHz  
200 MHz  
2.8  
166 MHz  
3.5  
133 MHz  
4.0  
Unit  
ns  
Maximum Access Time  
2.6  
325  
40  
Maximum Operating Current  
Maximum CMOS Standby Current  
265  
240  
225  
mA  
mA  
40  
40  
40  
Note  
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.  
Cypress Semiconductor Corporation  
Document #: 38-05516 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised May 22, 2007  
[+] Feedback  
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