CY7C1347F-200BZC

更新时间： 2024-11-24 22:15:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
19页	423K
描述
4-Mbit (128K x 36) Pipelined Sync SRAM

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CY7C1347F-200BZC 数据手册

CY7C1347F

4-Mbit (128K x 36) Pipelined Sync SRAM

Features

Functional Description^[1]

The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined

SRAM designed to support zero-wait-state secondary cache

with minimal glue logic.

• Fully registered inputs and outputs for pipelined oper-

ation

• 128K by 36 common I/O architecture

• 3.3V core power supply

• 2.5V/3.3V I/O operation

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.6 ns (for 225-MHz device)

— 2.8 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V

level, the I/O pins are 3.3V tolerant when V_DDQ= 2.5V.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

Maximum access delay from the clock rise is 2.6 ns (250-MHz

device)

CY7C1347F supports either the interleaved burst sequence

used by the Intel Pentium processor or a linear burst sequence

used by processors such as the PowerPC^®. The burst

sequence is selected through the MODE pin. Accesses can be

initiated by asserting either the Address Strobe from

Processor (ADSP) or the Address Strobe from Controller

(ADSC) at clock rise. Address advancement through the burst

sequence is controlled by the ADV input. A 2-bit on-chip

wraparound burst counter captures the first address in a burst

sequence and automatically increments the address for the

rest of the burst access.

• User-selectable burst counter supporting Intel^

Pentium^interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• JEDEC-standard 100-pin TQFP, 119-pin BGA and

165-pin fBGA packages

Byte write operations are qualified with the four Byte Write

Select (BW_[A:D]) inputs. A Global Write Enable (GW) overrides

all byte write inputs and writes data to all four bytes. All writes

are conducted with on-chip synchronous self-timed write

circuitry.

• “ZZ” Sleep Mode option and Stop Clock option

• Available in Industrial and Commercial temperature

ranges

Three synchronous Chip Selects (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to provide

proper data during depth expansion, OE is masked during the

first clock of a read cycle when emerging from a deselected

state.

Logic Block Diagram

A0, A1, A

ADDRESS

A[1:0]

MODE

ADV

CLK

BURST

COUNTER

AND

CLR

LOGIC

ADSC

ADSP

BYTE

WRITE REGISTER

D ,DQPD

BYTE

WRITE DRIVER

D ,DQPD

BWD

DQ^{C ,}DQP

BYTE

WRITE DRIVER

DQ^{C ,}DQP

BYTE

WRITE REGISTER

OUTPUT

BUFFERS

OUTPUT

REGISTERS

MEMORY

ARRAY

DQ s

SENSE

AMPS

DQP

DQ^{B ,}DQP

BYTE

WRITE DRIVER

DQ^{B ,}DQP

BYTE

WRITE REGISTER

DQPD

BYTE

WRITE DRIVER

A ,DQPA

BYTE

WRITE REGISTER

A ,DQPA

BWA

BWE

INPUT

REGISTERS

ENABLE

PIPELINED

ENABLE

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05213 Rev. *D

Revised April 9, 2004

12 3 4 5 6 7...19

中文翻译

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CY7C1347F-225AC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347F-225BGC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347F-250AC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347F-250BGC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G_11	CYPRESS	获取价格	4-Mbit (128 K x 36) Pipelined Sync SRAM Asynchronous output enable
CY7C1347G_12	CYPRESS	获取价格	4-Mbit (128 K Ã 36) Pipelined Sync SRAM
CY7C1347G_13	CYPRESS	获取价格	4-Mbit (128 K x 36) Pipelined Sync SRAM
CY7C1347G-133AXC	CYPRESS	获取价格	4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1347G-133AXCT	CYPRESS	获取价格	ZBT SRAM, 128KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-

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