Datasheet > CY7C1332AV25-200BGC

CY7C1332AV25-200BGC

更新时间： 2024-11-28 05:09:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
19页	394K
描述
18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late Write

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CY7C1330AV25

CY7C1332AV25

PRELIMINARY

18-Mbit (512K x 36/1Mbit x 18)

Pipelined Register-Register Late Write

Functional Description

Features

• Fast clock speed: 250, 200 MHz

• Fast access time: 2.0, 2.25 ns

The CY7C1330AV25 and CY7C1332AV25 are high perfor-

mance, Synchronous Pipelined SRAMs designed with late

write operation. These SRAMs can achieve speeds up to 250

• Synchronous Pipelined Operation with Self-timed Late

Write

MHz. Each memory cell consists of six transistors.

Late write feature avoids an idle cycle required during the

turnaround of the bus from a read to a write.

• Internally synchronized registered outputs eliminate

the need to control OE

All synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (K). The synchronous

inputs include all addresses (A), all data inputs (DQ_[a:d]), Chip

Enable (CE), Byte Write Selects (BWS_[a:d]), and read-write

control (WE). Read or Write Operations can be initiated with

the chip enable pin (CE). This signal allows the user to

select/deselect the device when desired.

• 2.5V core supply voltage

• 1.4–1.9V V_DDQsupply with V_REFof 0.68–0.95V

— Wide range HSTL I/O Levels

• Single Differential HSTL clock Input K and K

• Single WE (READ/WRITE) control pin

Power down feature is accomplished by pulling the

Synchronous signal ZZ HIGH.

• Individual byte write (BWS_[a:d]) control (may be tied

LOW)

Output Enable (OE) is an asynchronous input signal. OE can

be used to disable the outputs at any given time.

• Common I/O

• Asynchronous Output Enable Input

• Programmable Impedance Output Drivers

• JTAG boundary scan for BGA packaging version

Four pins are used to implement JTAG test capabilities. The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation.

• Available in a 119-ball BGA package (CY7C1330AV25

and CY7C1332AV25)

Configuration

CY7C1330AV25 – 512K x 36

CY7C1332AV25 – 1M x 18

Logic Block Diagram

Clock

Buffer

K,K

Data-In REG.

(2stage)

A_x

512Kx36

1Mx18

CONTROL

and WRITE

LOGIC

DQ_x

MEMORY

ARRAY

BWS_x

DQ_X

A_X

BWS_X

X = 18:0

512Kx36

1Mx18

X = a, b, c, d X = a, b, c, d

X = 19:0

X = a, b

Cypress Semiconductor Corporation

Document No: 001-07844 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 20, 2006

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与CY7C1332AV25-200BGC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1332AV25-200BGXC	CYPRESS	获取价格	18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late Write
CY7C1332AV25-250BGC	CYPRESS	获取价格	18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late Write
CY7C1332AV25-250BGXC	CYPRESS	获取价格	18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late Write
CY7C1333	CYPRESS	获取价格	64Kx32 Flow-Thru SRAM with NoBL⑩ Architecture
CY7C1333-50AC	CYPRESS	获取价格	64Kx32 Flow-Thru SRAM with NoBL⑩ Architecture
CY7C133-35JC	CYPRESS	获取价格	2K x 16 Dual-Port Static RAM
CY7C133-35JCT	CYPRESS	获取价格	Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C133-35JI	CYPRESS	获取价格	2K x 16 Dual-Port Static RAM
CY7C133-35JIR	CYPRESS	获取价格	Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C133-35JIT	CYPRESS	获取价格	Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68

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