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CY7C1333-50AC PDF预览

CY7C1333-50AC

更新时间： 2024-11-28 05:09:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
12页 183K
描述
64Kx32 Flow-Thru SRAM with NoBL⑩ Architecture

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中文翻译

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CY7C1333-50AC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数：100Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.81Is Samacsys：N
最长访问时间：14 ns其他特性：FLOW-THROUGH ARCHITECTURE
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：2097152 bit内存集成电路类型：ZBT SRAM
内存宽度：32湿度敏感等级：3
功能数量：1端子数量：100
字数：65536 words字数代码：64000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：64KX32
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：225
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.005 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.26 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

CY7C1333-50AC 数据手册

 浏览型号CY7C1333-50AC的Datasheet PDF文件第2页浏览型号CY7C1333-50AC的Datasheet PDF文件第3页浏览型号CY7C1333-50AC的Datasheet PDF文件第4页浏览型号CY7C1333-50AC的Datasheet PDF文件第5页浏览型号CY7C1333-50AC的Datasheet PDF文件第6页浏览型号CY7C1333-50AC的Datasheet PDF文件第7页 
CY7C1333  
64Kx32 Flow-Thru SRAM with NoBL™ Architecture  
Features  
Functional Description  
• Pin compatible and functionally equivalent to ZBT™  
device MT55L64L32F  
• Supports 66-MHz bus operations with zero wait states  
— Data is transferred on every clock  
The CY7C1333 is  
a 3.3V, 64K by 32 Synchronous  
Flow-Through Burst SRAM designed specifically to support  
unlimited true back-to-back Read/Write operations without the  
insertion of wait states. The CY7C1333 is equipped with the  
advanced No Bus Latency™ (NoBL™) logic required to en-  
able consecutive Read/Write operations with data being trans-  
ferred on every clock cycle. This feature dramatically improves  
the throughput of data through the SRAM, especially in sys-  
tems that require frequent Write-Read transitions. The  
CY7C1333 is pin/functionally compatible to ZBT SRAM  
MT55L64L32F.  
• Internally self-timed output buffer control to eliminate  
the need to use OE  
• Registered inputs for Flow-Through operation  
• Byte Write capability  
• 64K x 32 common I/O architecture  
• Single 3.3V power supply  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. The clock input is qualified by  
the Clock Enable (CEN) signal, which, when deasserted, sus-  
pends operation and extends the previous clock cycle. Maxi-  
mum access delay from the clock rise is 12.0 ns (66-MHz  
device).  
• Fast clock-to-output times  
— 12.0 ns (for 66-MHz device)  
— 14.0 ns (for 50-MHz device)  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed writes  
Write operations are controlled by the four Byte Write Select  
• Asynchronous output enable  
(BWS  
) and a Write Enable (WE) input. All writes are con-  
[0:3]  
• JEDEC-standard 100-pin TQFP package  
• Burst Capability—linear or interleaved burst order  
• Low (16.5 mW) standby power  
ducted with on-chip synchronous self-timed write circuitry.  
Three synchronous Chip Enables (CE , CE , CE ) and an  
1
2
3
asynchronous Output Enable (OE) provide for easy bank se-  
lection and output three-state control. In order to avoid bus  
contention, the output drivers are synchronously three-stated  
during the data portion of a write sequence.  
Logic Block Diagram  
32  
D
CLK  
Data-In REG.  
CE  
Q
32  
ADV/LD  
16  
A[15:0]  
CEN  
CE  
CONTROL  
and WRITE  
LOGIC  
32  
64KX  
MEMORY  
ARRAY  
32  
1
CE  
2
DQ[31:0]  
CE  
16  
3
32  
WE  
BWS  
[3:0]  
Mode  
OE  
Selection Guide  
7C1333-66  
12.0  
7C1333-50  
14.0  
Maximum Access Time (ns)  
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
Commercial  
Commercial  
310  
260  
5.0  
5.0  
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.  
ZBT is a trademark of Integrated Device Technology.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
August 4, 1999  
1234567...12

中文翻译

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与CY7C1333-50AC相关器件

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CY7C133-35JC CYPRESS

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 		2K x 16 Dual-Port Static RAM
CY7C133-35JCT CYPRESS

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 		Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C133-35JI CYPRESS

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 		2K x 16 Dual-Port Static RAM
CY7C133-35JIR CYPRESS

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 		Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C133-35JIT CYPRESS

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 		Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C1333-66AC CYPRESS

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 		64Kx32 Flow-Thru SRAM with NoBL⑩ Architecture
CY7C1333-66ACT CYPRESS

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 		ZBT SRAM, 64KX32, 12ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1333F-100AC CYPRESS

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 		ZBT SRAM, 64KX32, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1333H-133AXC CYPRESS

获取价格

 		ZBT SRAM, 64KX32, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, TQ
CY7C1333H-133AXI CYPRESS

获取价格

 		ZBT SRAM, 64KX32, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, TQ

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