Datasheet > CY7C1334-80AC

CY7C1334-80AC

更新时间： 2025-09-06 23:45:27

品牌	Logo	应用领域
其他 - ETC		内存集成电路静态存储器
页数	文件大小	规格书
12页	194K
描述
x32 Fast Synchronous SRAM

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CY7C1334-80AC 数据手册

334

CY7C1334

64Kx32 Pipelined SRAM with NoBL™ Architecture

• Low (16.5 mW) standby power

Features

Functional Description

• Pin compatible and functionally equivalent to ZBT™

device MT55L64L32P

The CY7C1334 is a 3.3V, 64K by 32 synchronous-pipelined

Burst SRAM designed specifically to support unlimited true

back-to-back Read/Write operations without the insertion of

wait states. The CY7C1334 is equipped with the advanced No

Bus Latency™ (NoBL™) logic required to enable consecutive

Read/Write operations with data being transferred on every

clock cycle. This feature dramatically improves the throughput

of the SRAM, especially in systems that require frequent

Write-Read transitions.The CY7C1334 is pin/functionally com-

patible to ZBT SRAM MT55L64L32P

• Supports 133-MHz bus operations with zero wait states

— Data is transferred on every clock

• Internally self-timed output buffer control to eliminate

the need to use OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write Capability

• 64K x 32 common I/O architecture

• Single 3.3V power supply

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal, which

when deasserted suspends operation and extends the previ-

ous clock cycle. Maximum access delay from the clock rise is

4.2 ns (133-MHz device).

• Fast clock-to-output times

— 4.2 ns (for 133-MHz device)

— 5.0 ns (for 100-MHz device)

— 7.0 ns (for 80-MHz device)

Write operations are controlled by the four Byte Write Selects

(BWS_[0-3]) and a Write Enable (WE) input. All writes are con-

ducted with on-chip synchronous self-timed write circuitry.

— 10.0 ns (for 50-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous output enable

• JEDEC-standard 100-pin TQFP package

• Burst Capability—linear or interleaved burst order

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

A_[15:0]

CEN

CONTROL

and WRITE

LOGIC

64KX

MEMORY

ARRAY

DQ_[31:0]

BWS

[3:0]

Selection Guide

7C1334-133

7C1334-100

7C1334-80

7.0

7C1334-50

Maximum Access Time (ns)

4.2

400

5.0

360

5.0

260

5.0

Maximum Operating Current (mA)

Commercial

310

Maximum CMOS Standby Current (mA)

5.0

No Bus Latency and NoBL are trademarks of Cypress Semiconductor.

ZBT is a trademark of Integrated Device Technology.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05065 Rev. **

Revised August 20, 2001

12 3 4 5 6 7...12

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与CY7C1334-80AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1334-80ACT	CYPRESS	获取价格	ZBT SRAM, 64KX32, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, TQFP-100
CY7C1334F-133AC	CYPRESS	获取价格	ZBT SRAM, 64KX32, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1334H	CYPRESS	获取价格	2-Mbit (64K x 32) Pipelined SRAM with NoBL⑩ A
CY7C1334H-133AXC	CYPRESS	获取价格	2-Mbit (64K x 32) Pipelined SRAM with NoBL⑩ A
CY7C1334H-133AXI	CYPRESS	获取价格	2-Mbit (64K x 32) Pipelined SRAM with NoBL⑩ A
CY7C1334H-166AXC	CYPRESS	获取价格	2-Mbit (64K x 32) Pipelined SRAM with NoBL⑩ A
CY7C1334H-166AXI	CYPRESS	获取价格	2-Mbit (64K x 32) Pipelined SRAM with NoBL⑩ A
CY7C1335-100AC	CYPRESS	获取价格	Cache SRAM, 32KX32, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1335-7NC	CYPRESS	获取价格	Cache SRAM, 32KX32, 7ns, CMOS, PQFP100
CY7C1335-8NC	CYPRESS	获取价格	Cache SRAM, 32KX32, CMOS, PQFP100

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