Datasheet > CY7C1333

CY7C1333

更新时间： 2024-11-28 05:09:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
12页	183K
描述
64Kx32 Flow-Thru SRAM with NoBL⑩ Architecture

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中文翻译

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CY7C1333 数据手册

CY7C1333

64Kx32 Flow-Thru SRAM with NoBL™ Architecture

Features

Functional Description

• Pin compatible and functionally equivalent to ZBT™

device MT55L64L32F

• Supports 66-MHz bus operations with zero wait states

— Data is transferred on every clock

The CY7C1333 is

a 3.3V, 64K by 32 Synchronous

Flow-Through Burst SRAM designed specifically to support

unlimited true back-to-back Read/Write operations without the

insertion of wait states. The CY7C1333 is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to en-

able consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data through the SRAM, especially in sys-

tems that require frequent Write-Read transitions. The

CY7C1333 is pin/functionally compatible to ZBT SRAM

MT55L64L32F.

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for Flow-Through operation

• Byte Write capability

• 64K x 32 common I/O architecture

• Single 3.3V power supply

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which, when deasserted, sus-

pends operation and extends the previous clock cycle. Maxi-

mum access delay from the clock rise is 12.0 ns (66-MHz

device).

• Fast clock-to-output times

— 12.0 ns (for 66-MHz device)

— 14.0 ns (for 50-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

Write operations are controlled by the four Byte Write Select

• Asynchronous output enable

(BWS

) and a Write Enable (WE) input. All writes are con-

[0:3]

• JEDEC-standard 100-pin TQFP package

• Burst Capability—linear or interleaved burst order

• Low (16.5 mW) standby power

ducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE , CE , CE ) and an

asynchronous Output Enable (OE) provide for easy bank se-

lection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Logic Block Diagram

CLK

Data-In REG.

ADV/LD

A_[15:0]

CEN

CONTROL

and WRITE

LOGIC

64KX

MEMORY

ARRAY

DQ_[31:0]

BWS

[3:0]

Mode

Selection Guide

7C1333-66

12.0

7C1333-50

14.0

Maximum Access Time (ns)

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Commercial

310

260

5.0

No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation.

ZBT is a trademark of Integrated Device Technology.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

August 4, 1999

12 3 4 5 6 7...12

中文翻译

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与CY7C1333相关器件

型号	品牌	获取价格	描述	数据表
CY7C1333-50AC	CYPRESS	获取价格	64Kx32 Flow-Thru SRAM with NoBL⑩ Architecture
CY7C133-35JC	CYPRESS	获取价格	2K x 16 Dual-Port Static RAM
CY7C133-35JCT	CYPRESS	获取价格	Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C133-35JI	CYPRESS	获取价格	2K x 16 Dual-Port Static RAM
CY7C133-35JIR	CYPRESS	获取价格	Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C133-35JIT	CYPRESS	获取价格	Dual-Port SRAM, 2KX16, 35ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C1333-66AC	CYPRESS	获取价格	64Kx32 Flow-Thru SRAM with NoBL⑩ Architecture
CY7C1333-66ACT	CYPRESS	获取价格	ZBT SRAM, 64KX32, 12ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1333F-100AC	CYPRESS	获取价格	ZBT SRAM, 64KX32, 8.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1333H-133AXC	CYPRESS	获取价格	ZBT SRAM, 64KX32, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, TQ

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