Datasheet > CY7C1150KV18-400BZXI

CY7C1150KV18-400BZXI

更新时间： 2024-04-09 18:40:59

品牌	Logo	应用领域
英飞凌 - INFINEON		双倍数据速率
页数	文件大小	规格书
29页	770K
描述
DDR-II+ CIO

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CY7C1150KV18-400BZXI 数据手册

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CY7C1148KV18/CY7C1150KV18

Truth Table

The truth table for the CY7C1148KV18, and CY7C1150KV18 follow. ^{[3, 4, 5, 6, 7, 8]}

Operation

R/W

Write cycle:

Load address; wait one cycle;

L–H

D(A) at K(t + 1)  D(A+1) at K(t + 1) 

input write data on consecutive K and K rising edges.

Read cycle: (2.0 cycle latency)

Load address; wait two cycles;

L–H

Q(A) at K(t + 2)

Q(A+1) at K(t + 2) 

read data on consecutive K and K rising edges.

NOP: No operation

L–H

High Z

Standby: Clock stopped

Stopped

Previous State

Write Cycle Descriptions

The write cycle description table for CY7C1148KV18 follows. ^{[3, 9]}

BWS₀BWS₁

Comments

L–H

–

During the data portion of a write sequence

CY7C1148KV18 both bytes (D_[17:0]) are written into the device.

–

L–H

–

L-H During the data portion of a write sequence:

CY7C1148KV18 both bytes (D_[17:0]) are written into the device.

–

During the data portion of a write sequence:

CY7C1148KV18 only the lower byte (D_[8:0]) is written into the device, D_[17:9]remains unaltered.

L–H During the data portion of a write sequence

CY7C1148KV18 only the lower byte (D_[8:0]) is written into the device, D_[17:9]remains unaltered.

L–H

–

During the data portion of a write sequence

CY7C1148KV18 only the upper byte (D_[17:9]) is written into the device, D_[8:0]remains unaltered.

L–H During the data portion of a write sequence

CY7C1148KV18 only the upper byte (D_[17:9]) is written into the device, D_[8:0]remains unaltered.

L–H

–

No data is written into the devices during this portion of a write operation.

L–H No data is written into the devices during this portion of a write operation.

Notes

3. X = ‘Don’t Care’, H = Logic HIGH, L = Logic LOW, represents rising edge.

4. Device powers up deselected with the outputs in a tristate condition.

5. ‘A’ represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.

6. ‘t’ represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.

7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.

8. Ensure that when clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.

9. Is based on a write cycle that was initiated in accordance with the Truth Table. BWS , BWS , BWS , and BWS can be altered on different portions of a write cycle, as

long as the setup and hold requirements are achieved.

Document Number: 001-58912 Rev. *I

Page 8 of 29

1...5 6 789 10 11...29

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与CY7C1150KV18-400BZXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1150KV18-450BZC	CYPRESS	获取价格	18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1150V18	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-300BZC	CYPRESS	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CY7C1150V18-300BZXC	CYPRESS	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, F
CY7C1150V18-300BZXI	CYPRESS	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, F
CY7C1150V18-333BZC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-333BZI	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-333BZXC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-333BZXI	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-375BZC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

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