Datasheet > CY7C1150KV18-400BZXI

CY7C1150KV18-400BZXI

更新时间： 2024-04-09 18:40:59

品牌	Logo	应用领域
英飞凌 - INFINEON		双倍数据速率
页数	文件大小	规格书
29页	770K
描述
DDR-II+ CIO

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数据手册

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CY7C1150KV18-400BZXI 数据手册

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CY7C1148KV18/CY7C1150KV18

Write Cycle Descriptions

The write cycle description table for CY7C1150KV18 follows. ^{[10, 11]}

BWS₀BWS₁BWS₂BWS₃

Comments

L–H

–

During the data portion of a write sequence, all four bytes (D_[35:0]) are written into

the device.

–

L–H

–

L–H During the data portion of a write sequence, all four bytes (D_[35:0]) are written into

the device.

–

During the data portion of a write sequence, only the lower byte (D_[8:0]) is written

into the device. D_[35:9]remains unaltered.

L–H During the data portion of a write sequence, only the lower byte (D_[8:0]) is written

into the device. D_[35:9]remains unaltered.

L–H

–

During the data portion of a write sequence, only the byte (D_[17:9]) is written into

the device. D_[8:0]and D_[35:18]remains unaltered.

L–H During the data portion of a write sequence, only the byte (D_[17:9]) is written into

the device. D_[8:0]and D_[35:18]remains unaltered.

L–H

–

During the data portion of a write sequence, only the byte (D_[26:18]) is written into

the device. D_[17:0]and D_[35:27]remains unaltered.

L–H During the data portion of a write sequence, only the byte (D_[26:18]) is written into

the device. D_[17:0]and D_[35:27]remains unaltered.

L–H

–

During the data portion of a write sequence, only the byte (D_[35:27]) is written into

the device. D_[26:0]remains unaltered.

L–H During the data portion of a write sequence, only the byte (D_[35:27]) is written into

the device. D_[26:0]remains unaltered.

L–H

–

No data is written into the device during this portion of a write operation.

L–H No data is written into the device during this portion of a write operation.

Notes

10. X = ‘Don’t Care’, H = Logic HIGH, L = Logic LOW, represents rising edge.

11. Is based on a write cycle that was initiated in accordance with the Truth Table on page 8. BWS , BWS , BWS , and BWS can be altered on different portions of a

write cycle, as long as the setup and hold requirements are achieved.

Document Number: 001-58912 Rev. *I

Page 9 of 29

1...6 7 8910 11 12...29

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与CY7C1150KV18-400BZXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C1150KV18-450BZC	CYPRESS	获取价格	18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1150V18	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-300BZC	CYPRESS	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CY7C1150V18-300BZXC	CYPRESS	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, F
CY7C1150V18-300BZXI	CYPRESS	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, F
CY7C1150V18-333BZC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-333BZI	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-333BZXC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-333BZXI	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-375BZC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

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