CY7C11461KV18, CY7C11571KV18
CY7C11481KV18, CY7C11501KV18
18-Mbit DDR II+ SRAM 2-Word Burst
Architecture (2.0 Cycle Read Latency)
18-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
Features
Functional Description
■ 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
■ 450 MHz Clock for High Bandwidth
The CY7C11461KV18, CY7C11571KV18, CY7C11481KV18,
and CY7C11501KV18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR II+ architecture. The DDR II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of K and K. Each address location is associated with two 8-bit
words (CY7C11461KV18), 9-bit words (CY7C11571KV18),
■ 2-word Burst for reducing Address Bus Frequency
■ Double Data Rate (DDR) Interfaces
(data transferred at 900 MHz) at 450 MHz
■ Available in 2.0 Clock Cycle Latency
■ Two Input Clocks (K and K) for Precise DDR Timing
❐ SRAM uses rising edges only
18-bit
words
(CY7C11481KV18),
or
36-bit
words
(CY7C11501KV18) that burst sequentially into or out of the
device.
■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
■ Data Valid Pin (QVLD) to indicate valid Data on the Output
■ Synchronous Internally Self Timed Writes
■ DDR II+ operates with 2.0 Cycle Read Latency when DOFF is
asserted HIGH
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■ Operates similar to DDR I Device with 1 Cycle Read Latency
when DOFF is asserted LOW
[1]
■ Core VDD = 1.8V ± 0.1V; I/O VDDQ = 1.4V to VDD
❐ Supports both 1.5V and 1.8V I/O supply
These devices are down bonded from the 65 nm 72M
QDRII+/DDRII+ devices and hence have the same IDD/ISB1
values and JTAG ID code as the equivalent 72M device options.
For details refer to the application note AN53189, 65 nm
Technology Interim QDRII+/DDRII+ SRAM Device Family
Description.
■ HSTL Inputs and Variable Drive HSTL Output Buffers
■ Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free Packages
■ JTAG 1149.1 compatible Test Access Port
Table 1. Selection Guide
450 400 375 333
Description
Unit
■ Phase Locked Loop (PLL) for Accurate Data Placement
MHz MHz MHz MHz
Maximum Operating
Frequency
450 400 375 333 MHz
Configurations
With Read cycle latency of 2.0 cycles:
CY7C11461KV18 – 2M x 8
Maximum Operating
Current
x8 630 580 550 510 mA
x9 630 580 550 510
x18 650 590 570 520
x36 820 750 710 640
CY7C11571KV18 – 2M x 9
CY7C11481KV18 – 1M x 18
CY7C11501KV18 – 512K x 36
Cypress Semiconductor Corporation
Document Number: 001-53198 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 31, 2011
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