Datasheet > CY7C1156V18-300BZXI

CY7C1156V18-300BZXI

更新时间： 2024-01-01 00:36:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
28页	1159K
描述
18-Mbit QDR⑩-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

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CY7C1156V18-300BZXI 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA, BGA165,11X15,40	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.84
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	300 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	15 mm	内存密度：	18874368 bit
内存集成电路类型：	QDR SRAM	内存宽度：	9
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	2097152 words
字数代码：	2000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	2MX9	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大待机电流：	0.201 A	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	0.663 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	20	宽度：	13 mm

CY7C1156V18-300BZXI 数据手册

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CY7C1141V18

CY7C1156V18

CY7C1143V18

CY7C1145V18

18-Mbit QDR™-II+ SRAM 4-Word Burst

Architecture (2.0 Cycle Read Latency)

Features

Functional Description

■ Separate Independent read and write data ports

❐ Supports concurrent transactions

■ 300 MHz to 375 MHz clock for high bandwidth

The CY7C1141V18, CY7C1156V18, CY7C1143V18, and

CY7C1145V18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR™-II+ architecture. QDR-II+ architecture

consists of two separate ports to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

operations. QDR-II+ architecture has separate data inputs and

data outputs to completely eliminate the need to “turn-around”

the data bus required with common IO devices. Access to each

■ 4-Word Burst for reducing address bus frequency

■ DoubleDataRate(DDR)interfacesonbothreadandwriteports

(data transferred at 750 MHz) at 375 MHz

■ Read latency of 2.0 clock cycles

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

port is accomplished through

a common address bus.

Addresses for read and write addresses are latched on alternate

rising edges of the input (K) clock. Accesses to the QDR-II+ read

and write ports are completely independent of one another. To

maximize data throughput, both read and write ports are

equipped with Double Data Rate (DDR) interfaces. Each

address location is associated with four 8-bit words

(CY7C1141V18), or 9-bit words (CY7C1156V18), or 18-bit words

(CY7C1143V18), or 36-bit words (CY7C1145V18) that burst

sequentially into or out of the device. Because data can be trans-

ferred into and out of the device on every rising edge of both input

clocks K and K, memory bandwidth is maximized while simpli-

fying system design by eliminating bus “turn-arounds”.

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate Port Selects for depth expansion

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency providing most current data

[1]

■ Core V_DD= 1.8V ± 0.1V; IO V_DDQ= 1.4V to V_DD

Depth expansion is accomplished with Port Selects for each port.

Port Selects enable each port to operate independently.

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.0 cycles:

CY7C1141V18 – 2M x 8

CY7C1156V18 – 2M x 9

CY7C1143V18 – 1M x 18

CY7C1145V18 – 512K x 36

Selection Guide

375 MHz

375

333 MHz

333

300 MHz

300

Unit

MHz

Maximum Operating Frequency

Maximum Operating Current

1020

920

850

Note

1. The QDR consortium specification for V

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V

DDQ

= 1.4V to V

Cypress Semiconductor Corporation

Document Number: 001-06583 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 15, 2007

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与CY7C1156V18-300BZXI相关器件

型号	品牌	描述	获取价格	数据表
CY7C1156V18-333BZC	CYPRESS	QDR SRAM, 2MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165	获取价格
CY7C1156V18-333BZI	CYPRESS	QDR SRAM, 2MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FPBGA-165	获取价格
CY7C11571KV18	CYPRESS	18-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)	获取价格
CY7C1157KV18	CYPRESS	18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)	获取价格
CY7C1157V18	CYPRESS	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)	获取价格
CY7C1157V18-300BZC	CYPRESS	DDR SRAM, 2MX9, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	获取价格

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