CY7C1148KV18/CY7C1150KV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
Input output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write
synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is driven
out on the rising edge of both the K and K clocks during read operations. When read access is deselected,
Q
[x:0] are automatically tri-stated.
CY7C1148KV18 DQ[17:0]
CY7C1150KV18 DQ[35:0]
LD
Input-
Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus
synchronous cycle sequence is defined. This definition includes address and read/write direction. All transactions
operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Byte Write Select 0, 1, 2, and 3 Active LOW. Sampled on the rising edge of the K and K clocks during
synchronous write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1148KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1150KV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls
D[35:27]
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
Input-
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 1M x 18 (2 arrays each of 512K x 18) for CY7C1148KV18, and 512K x 36 (2 arrays each
of 256K x 36) for CY7C1150KV18.
R/W
Input-
Synchronous Read or Write Input. When LD is LOW, this input designates the access type (read when
synchronous R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
QVLD
K
Valid output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
Input clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
Input clock Negative Input Clock Input. K is used to capture synchronous data being presented to the device and
K
to drive out data through Q[x:0]
.
CQ
Echo clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 22.
Echo clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
CQ
ZQ
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 22.
Input
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
DOFF
PLL Turn Off Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10 k or less pull up resistor. The device behaves in DDR I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with DDR I timing.
Document Number: 001-58912 Rev. *I
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