Datasheet > CY7C1150KV18-400BZXC

CY7C1150KV18-400BZXC

更新时间： 2024-11-24 09:43:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器双倍数据速率
页数	文件大小	规格书
29页	863K
描述
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

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CY7C1146KV18, CY7C1157KV18

CY7C1148KV18, CY7C1150KV18

18-Mbit DDR II+ SRAM Two-Word Burst

Architecture (2.0 Cycle Read Latency)

Features

Configurations

■ 18 Mbit density (2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36)

■ 450-MHz clock for high bandwidth

With Read Cycle Latency of 2.0 cycles:

CY7C1146KV18 – 2 M x 8

CY7C1157KV18 – 2 M x 9

■ Two-word burst for reducing address bus frequency

CY7C1148KV18 – 1 M x 18

CY7C1150KV18 – 512 K x 36

■ Double data rate (DDR) interfaces

(data transferred at 900 MHz) at 450 MHz

■ Available in 2.0 clock cycle latency

Functional Description

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

The CY7C1146KV18, CY7C1157KV18, CY7C1148KV18, and

CY7C1150KV18 are 1.8 V Synchronous Pipelined SRAMs

equipped with DDR II+ architecture. The DDR II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of K and K. Each address location is associated with two 8-bit

words (CY7C1146KV18), 9-bit words (CY7C1157KV18), 18-bit

words (CY7C1148KV18), or 36-bit words (CY7C1150KV18) that

burst sequentially into or out of the device.

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ DDR II+ operates with 2.0 cycle read latency when DOFF is

asserted HIGH

■ Operates similar to DDR I device with one cycle read latency

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

when DOFF is asserted LOW

[1]

■ Core V_DD= 1.8V ± 0.1 V; I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5 V and 1.8 V I/O supply

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ Phase-locked loop (PLL) for accurate data placement

Table 1. Selection Guide

Description

Maximum operating frequency

450 MHz

400 MHz

400

375 MHz

375

333 MHz

333

Unit

MHz

450

550

560

700

Maximum operating current

500

480

440

500

480

440

x18

x36

510

490

450

640

610

560

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4 V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-58912 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 24, 2011

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CY7C1150KV18-400BZXC 替代型号

型号	品牌	替代类型	描述	数据表
CY7C1170KV18-400BZXC	CYPRESS	完全替代	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1170KV18-400BZC	CYPRESS	完全替代	18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1150KV18-400BZC	CYPRESS	完全替代	18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

与CY7C1150KV18-400BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1150KV18-400BZXI	CYPRESS	获取价格	18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1150KV18-400BZXI	INFINEON	获取价格	DDR-II+ CIO
CY7C1150KV18-450BZC	CYPRESS	获取价格	18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1150V18	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-300BZC	CYPRESS	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
CY7C1150V18-300BZXC	CYPRESS	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, F
CY7C1150V18-300BZXI	CYPRESS	获取价格	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, F
CY7C1150V18-333BZC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-333BZI	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1150V18-333BZXC	CYPRESS	获取价格	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

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