Datasheet > CY7C1150KV18-400BZXI

CY7C1150KV18-400BZXI

更新时间： 2024-04-09 18:40:59

品牌	Logo	应用领域
英飞凌 - INFINEON		双倍数据速率
页数	文件大小	规格书
29页	770K
描述
DDR-II+ CIO

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CY7C1150KV18-400BZXI 数据手册

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CY7C1148KV18/CY7C1150KV18

18-Mbit DDR II+ SRAM Two-Word

Burst Architecture (2.0 Cycle Read Latency)

18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)

Features

Configurations

■ 18-Mbit density (1M × 18, 512K × 36)

■ 450-MHz clock for high bandwidth

With Read Cycle Latency of 2.0 cycles:

CY7C1148KV18 – 1M × 18

CY7C1150KV18 – 512K × 36

■ Two-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces (data transferred at

900 MHz) at 450 MHz

Functional Description

The CY7C1148KV18, and CY7C1150KV18 are 1.8

■ Available in 2.0 clock cycle latency

Synchronous Pipelined SRAMs equipped with DDR II+

architecture. The DDR II+ consists of an SRAM core with

advanced synchronous peripheral circuitry. Addresses for read

and write are latched on alternate rising edges of the input (K)

clock. Write data is registered on the rising edges of both K and

K. Read data is driven on the rising edges of K and K. Each

address location is associated with two 18-bit words

(CY7C1148KV18), or 36-bit words (CY7C1150KV18) that burst

sequentially into or out of the device.

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

■ DDR II+ operates with 2.0 cycle read latency when DOFF is

asserted HIGH

■ Operates similar to DDR I device with one cycle read latency

when DOFF is asserted LOW

[1]

■ Core V_DD= 1.8V ± 0.1 V; I/O V_DDQ= 1.4 V to V_DD

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

❐ Supports both 1.5 V and 1.8 V I/O supply

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

For a complete list of related documentation, click here.

■ Phase-locked loop (PLL) for accurate data placement

Selection Guide

Description

Maximum operating frequency

450 MHz

450

400 MHz Unit

400

510

640

MHz

Maximum operating current

× 18

× 36

560

700

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4 V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-58912 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 4, 2018

12 3 4 5 6 7...29

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与CY7C1150KV18-400BZXI相关器件

型号	品牌	描述	获取价格	数据表
CY7C1150KV18-450BZC	CYPRESS	18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)	获取价格
CY7C1150V18	CYPRESS	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)	获取价格
CY7C1150V18-300BZC	CYPRESS	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	获取价格
CY7C1150V18-300BZXC	CYPRESS	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, F	获取价格
CY7C1150V18-300BZXI	CYPRESS	DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, F	获取价格
CY7C1150V18-333BZC	CYPRESS	18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)	获取价格

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