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CY7C1069AV33_12 PDF预览

CY7C1069AV33_12

更新时间: 2024-11-29 12:50:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 445K
描述
2 M × 8 Static RAM

CY7C1069AV33_12 数据手册

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CY7C1069AV33  
2 M × 8 Static RAM  
2
M × 8 Static RAM  
Features  
Functional Description  
High speed  
tAA = 10 ns  
The CY7C1069AV33 is a high performance complementary  
metal oxide semiconductor (CMOS) static RAM organized as  
2,097,152 words by 8 bits. Writing to the device is accomplished  
by enabling the chip (by taking CE1 LOW and CE2 HIGH) and  
Write Enable (WE) inputs LOW.  
Low active power  
990 mW (max)  
Operating voltages of 3.3 ± 0.3 V  
2.0 V data retention  
Reading from the device is accomplished by enabling the chip  
(CE1 LOW and CE2 HIGH) as well as forcing the Output Enable  
(OE) LOW while forcing the WE HIGH. See “Truth Table” on  
page 8 for a complete description of Read and Write modes.  
Automatic power down when deselected  
TTL-compatible inputs and outputs  
Easy memory expansion with CE1 and CE2 features  
The input/output pins (I/O0 through I/O7) are placed in a high  
impedance state when the device is deselected (CE1 HIGH or  
CE2 LOW), the outputs are disabled (OE HIGH), or during a  
Write operation (CE1 LOW, CE2 HIGH, and WE LOW).  
Available in Pb-free 54-pin thin small outline package (TSOP) II  
package  
The CY7C1069AV33 is available in a 54-pin TSOP II package  
with center power and ground (revolutionary) pinout.  
Logic Block Diagram  
I/O  
0
Data in Drivers  
A
0
1
2
3
4
5
6
7
8
I/O  
1
A
A
A
I/O  
2
A
A
A
A
A
A
I/O  
3
2048K x 8  
ARRAY  
I/O  
9
10  
11  
4
A
A
A
I/O  
12  
5
I/O  
6
POWER  
DOWN  
COLUMN  
DECODER  
CE  
CE  
1
2
I/O  
WE  
OE  
7
Cypress Semiconductor Corporation  
Document Number: 38-05255 Rev. *J  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 29, 2010  
[+] Feedback  

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