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CY7C1061GN30-10ZXIT PDF预览

CY7C1061GN30-10ZXIT

更新时间: 2024-09-16 14:56:07
品牌 Logo 应用领域
英飞凌 - INFINEON 静态存储器
页数 文件大小 规格书
21页 1927K
描述
Asynchronous SRAM

CY7C1061GN30-10ZXIT 数据手册

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CY7C1061GN/CY7C10612GN  
16-Mbit (1M words × 16 bit) Static RAM  
16-Mbit (1M words  
× 16 bit) Static RAM  
Features  
Functional Description  
High speed  
tAA = 10 ns/15 ns  
The CY7C1061GN/CY7C10612GN is a high performance  
CMOS Static RAM organized as 1,048,576 words by 16 bits.  
To write to the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0 through  
Low active power  
ICC = 90 mA at 100 MHz  
Low CMOS standby current  
ISB2 = 20 mA (typ)  
A
19). If Byte High Enable (BHE) is LOW, then data from I/O pins  
(I/O8 through I/O15) is written into the location specified on the  
address pins (A0 through A19).  
Operating voltages of 2.2 V to 3.6 V  
1.0 V data retention  
To read from the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins appears  
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from  
memory appears on I/O8 to I/O15. See Truth Table on page 13  
for a complete description of Read and Write modes.  
Automatic power down when deselected  
TTL compatible inputs and outputs  
Easy memory expansion with CE1 and CE2 features  
Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball  
VFBGA packages  
The input or output pins (I/O0 through I/O15) are placed in a high  
impedance state when the device is deselected (CE1 HIGH/CE2  
LOW), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE1  
LOW, CE2 HIGH, and WE LOW).  
Offered in dual Chip Enable options  
Logic Block Diagram  
INPUT BUFFER  
A
0
A
1
A
2
A
4
3
I/O0 – I/O7  
I/O8 – I/O15  
1M x 16  
ARRAY  
A
A
5
A
6
A
7
A
8
A
9
COLUMN  
DECODER  
BHE  
WE  
CE2  
CE1  
OE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 001-93680 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised September 29, 2016  

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