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CY7C1049CV33-12ZSXA PDF预览

CY7C1049CV33-12ZSXA

更新时间: 2024-09-17 06:51:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
12页 886K
描述
4 Mbit (512K x 8) Static RAM

CY7C1049CV33-12ZSXA 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP44,.46,32
针数:44Reach Compliance Code:compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.23Is Samacsys:N
最长访问时间:12 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G44JESD-609代码:e4
长度:18.415 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:44字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP44,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified筛选级别:AEC-Q100
座面最大高度:1.194 mm最大待机电流:0.01 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.1 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:10.16 mmBase Number Matches:1

CY7C1049CV33-12ZSXA 数据手册

 浏览型号CY7C1049CV33-12ZSXA的Datasheet PDF文件第2页浏览型号CY7C1049CV33-12ZSXA的Datasheet PDF文件第3页浏览型号CY7C1049CV33-12ZSXA的Datasheet PDF文件第4页浏览型号CY7C1049CV33-12ZSXA的Datasheet PDF文件第5页浏览型号CY7C1049CV33-12ZSXA的Datasheet PDF文件第6页浏览型号CY7C1049CV33-12ZSXA的Datasheet PDF文件第7页 
CY7C1049CV33  
4 Mbit (512K x 8) Static RAM  
Features  
Functional Description  
Temperature ranges  
Commercial: 0°C to 70°C  
Industrial/Automotive -A: –40°C to 85°C  
Automotive-E: –40°C to 125°C  
The CY7C1049CV33 is a high performance CMOS Static RAM  
organized as 524,288 words by eight bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE), an  
active LOW Output Enable (OE), and three-state drivers. Writing  
to the device is accomplished by taking Chip Enable (CE) and  
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0  
through I/O7) is then written into the location specified on the  
address pins (A0 through A18).  
High Speed  
tAA = 10 ns  
Low Active Power  
324 mW (max)  
Reading from the device is accomplished by taking Chip Enable  
(CE) and Output Enable (OE) LOW while forcing Write Enable  
(WE) HIGH. Under these conditions, the contents of the memory  
location specified by the address pins appear on the I/O pins.  
2.0V Data Retention  
Automatic Power Down when Deselected  
TTL-compatible Inputs and Outputs  
Easy Memory Expansion with CE and OE features  
The eight input and output pins (I/O0 through I/O7) are placed in  
a high impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
The CY7C1049CV33 is available in standard 400-mil-wide  
36-pin SOJ package and 44-pin TSOP II package with center  
power and ground (revolutionary) pinout.  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
Logic Block Diagram  
A
0
IO  
0
INPUT BUFFER  
A
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
IO  
1
IO  
2
512K x 8  
ARRAY  
IO  
3
IO  
4
A
A
A
A
9
10  
11  
12  
IO  
5
IO  
6
CE  
IO  
POWER  
DOWN  
7
COLUMN DECODER  
WE  
OE  
Cypress Semiconductor Corporation  
Document #: 38-05006 Rev. *G  
198 Champion Court  
San Jose, CA 95134-1709  
•408-943-2600  
Revised January 07, 2010  
[+] Feedback  

CY7C1049CV33-12ZSXA 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1049CV33-12ZSXAT CYPRESS

完全替代

Standard SRAM, 512KX8, 12ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
AS7C34096A-12TIN ALSC

类似代替

3.3V 512K x 8 CMOS SRAM
71V424S12PHG IDT

功能相似

3.3V CMOS Static RAM

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