Datasheet > 71V424S12PHG

71V424S12PHG

更新时间： 2022-12-29 20:47:34

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
9页	72K
描述
3.3V CMOS Static RAM

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数据手册

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71V424S12PHG 数据手册

IDT71V424S

IDT71V424L

3.3V CMOS Static RAM

4 Meg (512K x 8-Bit)

Features

Description

◆

512K x 8 advanced high-speed CMOS Static RAM

JEDEC Center Power / GND pinout for reduced noise

Equal access and cycle times

TheIDT71V424isa4,194,304-bithigh-speedStaticRAMorganized

as512Kx8.Itisfabricatedusinghigh-perfomance,high-reliabilityCMOS

technology.Thisstate-of-the-arttechnology,combinedwithinnovative

circuitdesigntechniques,providesacost-effectivesolutionforhigh-speed

memoryneeds.

◆

— CommercialandIndustrial:10/12/15ns

Single 3.3V power supply

One Chip Select plus one Output Enable pin

Bidirectional data inputs and outputs directly

TTL-compatible

Low power consumption via chip deselect

Available in 36-pin, 400 mil plastic SOJ package and

44-pin, 400 mil TSOP.

◆

TheIDT71V424hasanoutputenablepinwhichoperatesasfastas

5ns,withaddressaccesstimesasfastas10ns.Allbidirectionalinputsand

outputs of the IDT71V424 are TTL-compatible and operation is from a

single3.3Vsupply.Fullystaticasynchronouscircuitryisused,requiring

no clocks or refresh for operation.

◆

TheIDT71V424ispackagedina36-pin,400milPlasticSOJand44-

pin, 400milTSOP.

FunctionalBlockDiagram

•

4,194,304-BIT

MEMORY ARRAY

ADDRESS

DECODER

•

A18

I/O0 - I/O7

I/O CONTROL

CONTROL

LOGIC

3622 drw 01

SEPTEMBER 2013

DSC-3622/10

12 3 4 5 6 7...9

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