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CY7C1006B-15VXCT PDF预览

CY7C1006B-15VXCT

更新时间: 2024-11-07 21:10:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
10页 163K
描述
Standard SRAM, 256KX4, 15ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, SOJ-28

CY7C1006B-15VXCT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOJ包装说明:SOJ,
针数:28Reach Compliance Code:compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.35最长访问时间:15 ns
JESD-30 代码:R-PDSO-J28JESD-609代码:e4
长度:17.907 mm内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:4
湿度敏感等级:3功能数量:1
端子数量:28字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX4封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:3.556 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:NICKEL PALLADIUM GOLD
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.5057 mmBase Number Matches:1

CY7C1006B-15VXCT 数据手册

 浏览型号CY7C1006B-15VXCT的Datasheet PDF文件第2页浏览型号CY7C1006B-15VXCT的Datasheet PDF文件第3页浏览型号CY7C1006B-15VXCT的Datasheet PDF文件第4页浏览型号CY7C1006B-15VXCT的Datasheet PDF文件第5页浏览型号CY7C1006B-15VXCT的Datasheet PDF文件第6页浏览型号CY7C1006B-15VXCT的Datasheet PDF文件第7页 
006B  
CY7C106B  
CY7C1006B  
256K x 4 Static RAM  
Enable (CE), an active LOW Output Enable (OE), and  
three-state drivers. These devices have an automatic pow-  
er-down feature that reduces power consumption by more  
than 65% when the devices are deselected.  
Features  
High speed  
— tAA = 12 ns  
CMOS for optimum speed/power  
Low active power  
Writing to the devices is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O  
pins (I/O0 through I/O3) is then written into the location speci-  
fied on the address pins (A0 through A17).  
495 mW  
Low standby power  
275 mW  
Reading from the devices is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the four I/O pins.  
2.0V data retention (optional)  
100 µW  
Automatic power-down when deselected  
TTL-compatible inputs and outputs  
The four input/output pins (I/O0 through I/O3) are placed in a  
high-impedance state when the devices are deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE and WE LOW).  
Functional Description  
The CY7C106B and CY7C1006B are high-performance  
CMOS static RAMs organized as 262,144 words by 4 bits.  
Easy memory expansion is provided by an active LOW Chip  
The CY7C106B is available in a standard 400-mil-wide SOJ;  
the CY7C1006B is available in a standard 300-mil-wide SOJ.  
Logic Block Diagram  
Pin Configuration  
SOJ  
Top View  
28  
27  
26  
1
2
3
4
5
6
A
V
CC  
0
A
A
17  
A
16  
A
15  
1
A
2
3
A
25  
24  
A
A
14  
A
13  
A
12  
4
23  
22  
A
5
A
7
8
9
10  
11  
12  
13  
6
A
21  
20  
19  
18  
17  
A
7
11  
INPUTBUFFER  
A
NC  
I/O  
8
A
9
3
2
1
A
1
A
10  
I/O  
I/O  
I/O  
A
A
3
I/O  
I/O  
I/O  
I/O  
CE  
OE  
GND  
2
3
2
1
0
16  
15  
0
14  
WE  
A
4
A
5
512 x 512 x 4  
ARRAY  
C106B2  
A
6
A
7
A
8
A
9
POWER  
DOWN  
COLUMN  
DECODER  
CE  
WE  
OE  
C106B1  
Selection Guide  
7C106B-12  
7C1006B-12  
7C106B-15  
7C1006B-15  
7C106B-20  
7C1006B-20  
7C106B-25  
7C1006B-25  
7C106B-35  
Maximum Access Time (ns)  
12  
90  
15  
80  
20  
75  
25  
70  
35  
60  
Maximum Operating  
Current (mA)  
Maximum Standby  
Current (mA)  
50  
30  
30  
30  
25  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05037 Rev. **  
Revised August 24, 2001  

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