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CY7C1007 PDF预览

CY7C1007

更新时间: 2024-11-07 05:09:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
8页 144K
描述
1M x 1 Static RAM

CY7C1007 数据手册

 浏览型号CY7C1007的Datasheet PDF文件第2页浏览型号CY7C1007的Datasheet PDF文件第3页浏览型号CY7C1007的Datasheet PDF文件第4页浏览型号CY7C1007的Datasheet PDF文件第5页浏览型号CY7C1007的Datasheet PDF文件第6页浏览型号CY7C1007的Datasheet PDF文件第7页 
CY7C107  
CY7C1007  
1M x 1 Static RAM  
memory expansion is provided by an active LOW Chip Enable  
(CE) and three-state drivers. These devices have an automatic  
power-down feature that reduces power consumption by more  
than 65% when deselected.  
Features  
• High speed  
— t = 12 ns  
AA  
Writing to the devices is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the input pin  
• CMOS for optimum speed/power  
• Low active power  
— 825 mW  
(D ) is written into the memory location specified on the ad-  
IN  
dress pins (A through A ).  
0
19  
• Low standby power  
— 275 mW  
Reading from the devices is accomplished by taking Chip En-  
able (CE) LOW while Write Enable (WE) remains HIGH. Under  
these conditions, the contents of the memory location speci-  
• 2.0V data retention (optional)  
fied by the address pins will appear on the data output (D  
pin.  
)
OUT  
100  
W
µ
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
The output pin (D  
) is placed in a high-impedance state  
OUT  
when the device is deselected (CE HIGH) or during a write  
operation (CE and WE LOW).  
Functional Description  
The CY7C107 and CY7C1007 are high-performance CMOS  
static RAMs organized as 1,048,576 words by 1 bit. Easy  
The CY7C107 is available in a standard 400-mil-wide SOJ; the  
CY7C1007 is available in a standard 300-mil-wide SOJ.  
Logic Block Diagram  
Pin Configuration  
SOJ  
Top View  
D
IN  
28  
27  
26  
1
2
3
4
5
6
A
A
A
A
A
A
V
CC  
10  
11  
12  
13  
14  
15  
A
9
A
8
25  
24  
A
7
INPUT BUFFER  
A
6
A
A0  
23  
22  
5
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
7
8
9
10  
11  
12  
13  
NC  
A
4
21  
20  
19  
18  
17  
A
17  
NC  
16  
A
A
3
A
19  
A
2
18  
512x2048  
ARRAY  
A
A
1
D
OUT  
A
0
D
OUT  
WE  
GND  
16  
15  
D
IN  
14  
CE  
107-2  
POWER  
DOWN  
COLUMN  
DECODER  
CE  
WE  
107-1  
Selection Guide  
7C107-12  
7C107-15  
7C107-20  
7C107-25  
7C1007-12  
7C1007-15  
7C1007-20  
7C1007-25  
7C107-35  
35  
Maximum Access Time (ns)  
12  
15  
20  
25  
Maximum Operating  
Current (mA)  
150  
135  
125  
120  
110  
Maximum Standby  
Current (mA)  
50  
40  
30  
30  
25  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
December 1992 – Revised September 3, 1999  

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