5秒后页面跳转
CY7C1006L-15VC PDF预览

CY7C1006L-15VC

更新时间: 2024-11-08 09:36:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管
页数 文件大小 规格书
9页 251K
描述
Standard SRAM, 256KX4, 15ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28

CY7C1006L-15VC 数据手册

 浏览型号CY7C1006L-15VC的Datasheet PDF文件第2页浏览型号CY7C1006L-15VC的Datasheet PDF文件第3页浏览型号CY7C1006L-15VC的Datasheet PDF文件第4页浏览型号CY7C1006L-15VC的Datasheet PDF文件第5页浏览型号CY7C1006L-15VC的Datasheet PDF文件第6页浏览型号CY7C1006L-15VC的Datasheet PDF文件第7页 
006  
CY7C106  
CY7C1006  
256K x 4 Static RAM  
an active LOW output enable (OE), and three-state drivers.  
These devices have an automatic power-down feature that re-  
duces power consumption by more than 65% when the devic-  
es are deselected.  
Features  
• High speed  
— tAA = 12 ns  
• CMOS for optimum speed/power  
• Low active power  
Writing to the devices is accomplished by taking chip enable  
(CE) and write enable (WE) inputs LOW. Data on the four I/O  
pins (I/O0 through I/O3) is then written into the location speci-  
fied on the address pins (A0 through A17).  
— 910 mW  
• Low standby power  
— 275 mW  
Reading from the devices is accomplished by taking chip en-  
able (CE) and output enable (OE) LOW while forcing write en-  
able (WE) HIGH. Under these conditions, the contents of the  
memory location specified by the address pins will appear on  
the four I/O pins.  
• 2.0V data retention (optional)  
100 µW  
Automatic power-down when deselected  
TTL-compatible inputs and outputs  
The four input/output pins (I/O0 through I/O3) are placed in a  
high-impedance state when the devices are deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE and WE LOW).  
Functional Description  
The CY7C106 and CY7C1006 are high-performance CMOS  
static RAMs organized as 262,144 words by 4 bits. Easy mem-  
ory expansion is provided by an active LOW chip enable (CE),  
The CY7C106 is available in a standard 400-mil-wide SOJ; the  
CY7C1006 is available in a standard 300-mil-wide SOJ.  
Logic Block Diagram  
Pin Configuration  
SOJ  
Top View  
28  
27  
26  
1
2
3
4
5
6
A
V
CC  
0
A
A
17  
A
16  
A
15  
1
A
2
3
A
25  
24  
A
A
14  
A
13  
A
12  
4
23  
22  
A
5
A
7
8
9
10  
11  
12  
13  
6
A
21  
20  
19  
18  
17  
A
7
11  
INPUTBUFFER  
A
NC  
I/O  
8
A
9
3
2
1
A
1
A
10  
I/O  
I/O  
I/O  
A
A
3
I/O  
I/O  
I/O  
I/O  
CE  
OE  
GND  
2
3
2
1
0
16  
15  
0
14  
WE  
A
4
A
5
512 x 512 x 4  
ARRAY  
C1062  
A
6
A
7
A
8
A
9
POWER  
DOWN  
COLUMN  
DECODER  
CE  
WE  
OE  
C1061  
Selection Guide  
7C106-12  
7C1006-12  
7C106-15  
7C1006-15  
7C106-20  
7C1006-20  
7C106-25  
7C1006-25  
7C106-35  
35  
Maximum Access Time (ns)  
12  
15  
20  
25  
Maximum Operating  
Current (mA)  
165  
155  
145  
130  
125  
Maximum Standby  
Current (mA)  
50  
30  
30  
30  
25  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05033 Rev. **  
Revised July 9, 1998  

与CY7C1006L-15VC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1006L-15VCR CYPRESS

获取价格

Standard SRAM, 256KX4, 15ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28
CY7C1006L-20VCT CYPRESS

获取价格

Standard SRAM, 256KX4, 20ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28
CY7C1007 CYPRESS

获取价格

1M x 1 Static RAM
CY7C1007-12PC ETC

获取价格

x1 SRAM
CY7C1007-12VC CYPRESS

获取价格

1M x 1 Static RAM
CY7C1007-15DC ETC

获取价格

x1 SRAM
CY7C1007-15DMB ETC

获取价格

x1 SRAM
CY7C1007-15PC ETC

获取价格

x1 SRAM
CY7C1007-15VC CYPRESS

获取价格

1M x 1 Static RAM
CY7C1007-15VCR CYPRESS

获取价格

Standard SRAM, 1MX1, 15ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28